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verilog_lecture/lab/lab1
verilog_lecture/lab/lab10/test_pli.v
verilog_lecture/lab/lab10/veriuser.c
verilog_lecture/lab/lab10
verilog_lecture/lab/lab4/clk_chain.sdf
verilog_lecture/lab/lab4/clk_chain.v
verilog_lecture/lab/lab4
verilog_lecture/lab/lab5/case.v
verilog_lecture/lab/lab5/design.sdf
verilog_lecture/lab/lab5/design.v
verilog_lecture/lab/lab5/ifthen.v
verilog_lecture/lab/lab5/multi_bit_access.v
verilog_lecture/lab/lab5/single_word_access.v
verilog_lecture/lab/lab5
verilog_lecture/lab/lab9/violation.v
verilog_lecture/lab/lab9
verilog_lecture/lab
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verilog_lecture/lab_solution/lab1
verilog_lecture/lab_solution/lab2/add16.v
verilog_lecture/lab_solution/lab2/mulitplier.v
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verilog_lecture/lab_solution/lab2/top.v
verilog_lecture/lab_solution/lab2
verilog_lecture/lab_solution/lab3/lab3.v
verilog_lecture/lab_solution/lab3
verilog_lecture/lab_solution/lab4/clk_chain.sdf
verilog_lecture/lab_solution/lab4/clk_chain.v
verilog_lecture/lab_solution/lab4
verilog_lecture/lab_solution/lab5/case.v
verilog_lecture/lab_solution/lab5/design.sdf
verilog_lecture/lab_solution/lab5/design.v
verilog_lecture/lab_solution/lab5/ifthen.v
verilog_lecture/lab_solution/lab5/multi_bit_access.v
verilog_lecture/lab_solution/lab5/single_word_access.v
verilog_lecture/lab_solution/lab5
verilog_lecture/lab_solution/lab6/add16.v
verilog_lecture/lab_solution/lab6/mulitplier_add.v
verilog_lecture/lab_solution/lab6/top.v
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verilog_lecture/lab_solution/lab7/binary/state.v
verilog_lecture/lab_solution/lab7/binary/top.v
verilog_lecture/lab_solution/lab7/binary
verilog_lecture/lab_solution/lab7/one-hot/state_onehot.v
verilog_lecture/lab_solution/lab7/one-hot/top_onehot.v
verilog_lecture/lab_solution/lab7/one-hot
verilog_lecture/lab_solution/lab7
verilog_lecture/lab_solution/lab8/initial.v
verilog_lecture/lab_solution/lab8
verilog_lecture/lab_solution/lab9/mux2.v
verilog_lecture/lab_solution/lab9/violation.v
verilog_lecture/lab_solution/lab9
verilog_lecture/lab_solution
verilog_lecture/verilog_lecture.ppt
verilog_lecture