“Randomized Smoothing Networks” introduced the idea of using networks composed of a type of comparator/memory element, initialized to random initial states, to create smoothing networks, which take arbitrary input loads into the network and produce an output that balances the load among all the outputs in a predictable manner. I created a synthesizable Verilog model of these comparator/memory elements (or “balancers”), and used a pseudo-random linear feedback shift register (LFSR) to toggle all possible initial random states for two of the proposed RSNs configurations, the Block network and the Butterfly network, verifying the results of Herlihy and Tirthapura.