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文件名称:6_Sets_of_8051_VHDL_Verilog

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    1.14mb
  • 已下载：
    0次
  • 提 供 者：
    z***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

it has 6 packages of 8051 sources,including source code(VHDL and Verilog),dc scr ipts, pdfs, netlists etc. and a MIPS IP package
(系统自动生成,下载前可以参看下载内容)

下载文件列表

5_Sets_of_8051_VHDL_Verilog/MIPS_IP/alu.vhd
5_Sets_of_8051_VHDL_Verilog/MIPS_IP/alucontrol.vhd
5_Sets_of_8051_VHDL_Verilog/MIPS_IP/control.vhd
5_Sets_of_8051_VHDL_Verilog/MIPS_IP/datapath.vhd
5_Sets_of_8051_VHDL_Verilog/MIPS_IP/dff32.vhd
5_Sets_of_8051_VHDL_Verilog/MIPS_IP/leo_mips.vhd
5_Sets_of_8051_VHDL_Verilog/MIPS_IP/leo_mips_p.vhd
5_Sets_of_8051_VHDL_Verilog/MIPS_IP/mips_clkdiv.vhd
5_Sets_of_8051_VHDL_Verilog/MIPS_IP/mips_core.vhd
5_Sets_of_8051_VHDL_Verilog/MIPS_IP/mips_ram.vhd
5_Sets_of_8051_VHDL_Verilog/MIPS_IP/mips_rom.vhd
5_Sets_of_8051_VHDL_Verilog/MIPS_IP/output.coe
5_Sets_of_8051_VHDL_Verilog/MIPS_IP/regfile.vhd
5_Sets_of_8051_VHDL_Verilog/MIPS_IP/wr_we.vhd
5_Sets_of_8051_VHDL_Verilog/DW8051_Verilog/DW01_add.v
5_Sets_of_8051_VHDL_Verilog/DW8051_Verilog/DW01_addsub.v
5_Sets_of_8051_VHDL_Verilog/DW8051_Verilog/DW01_cmp2.v
5_Sets_of_8051_VHDL_Verilog/DW8051_Verilog/DW01_sub.v
5_Sets_of_8051_VHDL_Verilog/DW8051_Verilog/DW02_mult.v
5_Sets_of_8051_VHDL_Verilog/DW8051_Verilog/DW8051_alu.v
5_Sets_of_8051_VHDL_Verilog/DW8051_Verilog/DW8051_biu.v
5_Sets_of_8051_VHDL_Verilog/DW8051_Verilog/DW8051_control.v
5_Sets_of_8051_VHDL_Verilog/DW8051_Verilog/DW8051_core.v
5_Sets_of_8051_VHDL_Verilog/DW8051_Verilog/DW8051_cpu.v
5_Sets_of_8051_VHDL_Verilog/DW8051_Verilog/DW8051_intr_0.v
5_Sets_of_8051_VHDL_Verilog/DW8051_Verilog/DW8051_intr_1.v
5_Sets_of_8051_VHDL_Verilog/DW8051_Verilog/DW8051_main_regs.v
5_Sets_of_8051_VHDL_Verilog/DW8051_Verilog/DW8051_op_decoder.v
5_Sets_of_8051_VHDL_Verilog/DW8051_Verilog/DW8051_serial.v
5_Sets_of_8051_VHDL_Verilog/DW8051_Verilog/DW8051_shftreg.v
5_Sets_of_8051_VHDL_Verilog/DW8051_Verilog/DW8051_timer.v
5_Sets_of_8051_VHDL_Verilog/DW8051_Verilog/DW8051_timer2.v
5_Sets_of_8051_VHDL_Verilog/DW8051_Verilog/DW8051_timer_ctr.v
5_Sets_of_8051_VHDL_Verilog/DW8051_Verilog/DW8051_updn_ctr.v
5_Sets_of_8051_VHDL_Verilog/DW8051_Verilog/DW8051_u_ctr_clr.v
5_Sets_of_8051_VHDL_Verilog/DW8051_Verilog/transcript
5_Sets_of_8051_VHDL_Verilog/DW8051_Verilog/DW8051/DW8051_package.inc
5_Sets_of_8051_VHDL_Verilog/DW8051_Verilog/DW8051/DW8051_parameter.v
5_Sets_of_8051_VHDL_Verilog/DW8051_Verilog/DW8051/vssver.scc
5_Sets_of_8051_VHDL_Verilog/8086IP/alu.vhd
5_Sets_of_8051_VHDL_Verilog/8086IP/a_table.vhd
5_Sets_of_8051_VHDL_Verilog/8086IP/biu.vhd
5_Sets_of_8051_VHDL_Verilog/8086IP/biufsm.vhd
5_Sets_of_8051_VHDL_Verilog/8086IP/cpu86.vhd
5_Sets_of_8051_VHDL_Verilog/8086IP/cpu86instr.vhd
5_Sets_of_8051_VHDL_Verilog/8086IP/cpu86pack.vhd
5_Sets_of_8051_VHDL_Verilog/8086IP/datapath.vhd
5_Sets_of_8051_VHDL_Verilog/8086IP/dataregfile.vhd
5_Sets_of_8051_VHDL_Verilog/8086IP/divider.vhd
5_Sets_of_8051_VHDL_Verilog/8086IP/d_table.vhd
5_Sets_of_8051_VHDL_Verilog/8086IP/formatter.vhd
5_Sets_of_8051_VHDL_Verilog/8086IP/hwmfsm.vhd
5_Sets_of_8051_VHDL_Verilog/8086IP/hwmon.vhd
5_Sets_of_8051_VHDL_Verilog/8086IP/ipregister.vhd
5_Sets_of_8051_VHDL_Verilog/8086IP/multiplier.vhd
5_Sets_of_8051_VHDL_Verilog/8086IP/m_table.vhd
5_Sets_of_8051_VHDL_Verilog/8086IP/n_table.vhd
5_Sets_of_8051_VHDL_Verilog/8086IP/proc.vhd
5_Sets_of_8051_VHDL_Verilog/8086IP/regshiftmux.vhd
5_Sets_of_8051_VHDL_Verilog/8086IP/r_table.vhd
5_Sets_of_8051_VHDL_Verilog/8086IP/segregfile.vhd
5_Sets_of_8051_VHDL_Verilog/8086IP/top.vhd
5_Sets_of_8051_VHDL_Verilog/8051_VerilogSource/syn/src/verilog/disp.v
5_Sets_of_8051_VHDL_Verilog/8051_VerilogSource/syn/src/verilog/oc8051_fpga_top.v
5_Sets_of_8051_VHDL_Verilog/8051_VerilogSource/syn/src/verilog/oc8051_ram.v
5_Sets_of_8051_VHDL_Verilog/8051_VerilogSource/syn/src/verilog/oc8051_rom.v
5_Sets_of_8051_VHDL_Verilog/8051_VerilogSource/syn/src/verilog/read me.txt
5_Sets_of_8051_VHDL_Verilog/8051_VerilogSource/syn/out/oc8051.ucf
5_Sets_of_8051_VHDL_Verilog/8051_VerilogSource/syn/out/oc8051_top.bit
5_Sets_of_8051_VHDL_Verilog/8051_VerilogSource/syn/out/oc8051_top.srm
5_Sets_of_8051_VHDL_Verilog/8051_VerilogSource/syn/out/oc8051_top.srs
5_Sets_of_8051_VHDL_Verilog/8051_VerilogSource/syn/out/read.me
5_Sets_of_8051_VHDL_Verilog/8051_VerilogSource/syn/log/oc8051_top.srr
5_Sets_of_8051_VHDL_Verilog/8051_VerilogSource/sim/rtl_sim/src/verilog/oc8051_ram.v
5_Sets_of_8051_VHDL_Verilog/8051_VerilogSource/sim/rtl_sim/src/verilog/oc8051_rom.v
5_Sets_of_8051_VHDL_Verilog/8051_VerilogSource/sim/rtl_sim/run/MAKE
5_Sets_of_8051_VHDL_Verilog/8051_VerilogSource/sim/rtl_sim/run/make_fpga
5_Sets_of_8051_VHDL_Verilog/8051_VerilogSource/sim/rtl_sim/out/VERILOG.LOG
5_Sets_of_8051_VHDL_Verilog/8051_VerilogSource/bench/verilog/oc8051_defines.v
5_Sets_of_8051_VHDL_Verilog/8051_VerilogSource/bench/verilog/oc8051_fpga_tb.v
5_Sets_of_8051_VHDL_Verilog/8051_VerilogSource/bench/verilog/oc8051_tb.v
5_Sets_of_8051_VHDL_Verilog/8051_VerilogSource/bench/verilog/oc8051_timescale.v
5_Sets_of_8051_VHDL_Verilog/8051_VerilogSource/asm/test.asm
5_Sets_of_8051_VHDL_Verilog/8051_VerilogSource/8051_rtl/verilog/oc8051_acc.v
5_Sets_of_8051_VHDL_Verilog/8051_VerilogSource/8051_rtl/verilog/oc8051_alu.v
5_Sets_of_8051_VHDL_Verilog/8051_VerilogSource/8051_rtl/verilog/oc8051_alu_src1_sel.v
5_Sets_of_8051_VHDL_Verilog/8051_VerilogSource/8051_rtl/verilog/oc8051_alu_src2_sel.v
5_Sets_of_805

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