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文件名称:time4clock2

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [C/C++] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    577.94kb
  • 已下载：
    0次
  • 提 供 者：
    g*****
  • 相关连接：
    无
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

秒表/时钟计时器是在一种计时器上实现两种基本功能的一种器件。它广泛应用于各种场所，同时，它以其小巧，价格低廉，走时精度高，使用方便，功能多，便于集成化。-Stopwatch/clock timer is a device on a timer to achieve two basic functions. It is widely used in various places, the same time, its compact, low cost, travel time and high precision, easy to use, multi-functional, easy to integrated.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

time4clock2/cons.ucf
time4clock2/fuse.log
time4clock2/fuse.xmsgs
time4clock2/fuseRelaunch.cmd
time4clock2/iseconfig/time4clock2.projectmgr
time4clock2/iseconfig/time4clock2.xreport
time4clock2/isim/isim_usage_statistics.html
time4clock2/isim/pn_info
time4clock2/isim/test_isim_beh.exe.sim/isimcrash.log
time4clock2/isim/test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
time4clock2/isim/test_isim_beh.exe.sim/isimkernel.log
time4clock2/isim/test_isim_beh.exe.sim/netId.dat
time4clock2/isim/test_isim_beh.exe.sim/test_isim_beh.exe
time4clock2/isim/test_isim_beh.exe.sim/tmp_save/_1
time4clock2/isim/test_isim_beh.exe.sim/work/m_00000000002380014857_2626377370.c
time4clock2/isim/test_isim_beh.exe.sim/work/m_00000000002380014857_2626377370.didat
time4clock2/isim/test_isim_beh.exe.sim/work/m_00000000002380014857_2626377370.nt.obj
time4clock2/isim/test_isim_beh.exe.sim/work/m_00000000003489247350_1985558087.c
time4clock2/isim/test_isim_beh.exe.sim/work/m_00000000003489247350_1985558087.didat
time4clock2/isim/test_isim_beh.exe.sim/work/m_00000000003489247350_1985558087.nt.obj
time4clock2/isim/test_isim_beh.exe.sim/work/m_00000000004093713498_2073120511.c
time4clock2/isim/test_isim_beh.exe.sim/work/m_00000000004093713498_2073120511.didat
time4clock2/isim/test_isim_beh.exe.sim/work/m_00000000004093713498_2073120511.nt.obj
time4clock2/isim/test_isim_beh.exe.sim/work/test_isim_beh.exe_main.c
time4clock2/isim/test_isim_beh.exe.sim/work/test_isim_beh.exe_main.nt.obj
time4clock2/isim/work/glbl.sdb
time4clock2/isim/work/test.sdb
time4clock2/isim/work/time4clock2.sdb
time4clock2/isim.cmd
time4clock2/isim.log
time4clock2/test.v
time4clock2/test_beh.prj
time4clock2/test_isim_beh.exe
time4clock2/test_isim_beh.wdb
time4clock2/time4clock2.bld
time4clock2/time4clock2.cmd_log
time4clock2/time4clock2.gise
time4clock2/time4clock2.lso
time4clock2/time4clock2.ngc
time4clock2/time4clock2.ngd
time4clock2/time4clock2.ngr
time4clock2/time4clock2.prj
time4clock2/time4clock2.stx
time4clock2/time4clock2.syr
time4clock2/time4clock2.v
time4clock2/time4clock2.xise
time4clock2/time4clock2.xst
time4clock2/time4clock2_envsettings.html
time4clock2/time4clock2_map.map
time4clock2/time4clock2_map.mrp
time4clock2/time4clock2_ngdbuild.xrpt
time4clock2/time4clock2_summary.html
time4clock2/time4clock2_xst.xrpt
time4clock2/wave_gen_ver_s6/clkx_bus.v
time4clock2/wave_gen_ver_s6/clk_div.v
time4clock2/wave_gen_ver_s6/clk_gen.v
time4clock2/wave_gen_ver_s6/clogb2.txt
time4clock2/wave_gen_ver_s6/cmd_parse.v
time4clock2/wave_gen_ver_s6/dac_spi.v
time4clock2/wave_gen_ver_s6/debouncer.v
time4clock2/wave_gen_ver_s6/fuse.log
time4clock2/wave_gen_ver_s6/fuse.xmsgs
time4clock2/wave_gen_ver_s6/fuseRelaunch.cmd
time4clock2/wave_gen_ver_s6/ipcore_dir/blk_mem_gen_readme.txt
time4clock2/wave_gen_ver_s6/ipcore_dir/char_fifo.asy
time4clock2/wave_gen_ver_s6/ipcore_dir/char_fifo.gise
time4clock2/wave_gen_ver_s6/ipcore_dir/char_fifo.ncf
time4clock2/wave_gen_ver_s6/ipcore_dir/char_fifo.ngc
time4clock2/wave_gen_ver_s6/ipcore_dir/char_fifo.sym
time4clock2/wave_gen_ver_s6/ipcore_dir/char_fifo.v
time4clock2/wave_gen_ver_s6/ipcore_dir/char_fifo.veo
time4clock2/wave_gen_ver_s6/ipcore_dir/char_fifo.vhd
time4clock2/wave_gen_ver_s6/ipcore_dir/char_fifo.vho
time4clock2/wave_gen_ver_s6/ipcore_dir/char_fifo.xco
time4clock2/wave_gen_ver_s6/ipcore_dir/char_fifo.xise
time4clock2/wave_gen_ver_s6/ipcore_dir/char_fifo_flist.txt
time4clock2/wave_gen_ver_s6/ipcore_dir/char_fifo_readme.txt
time4clock2/wave_gen_ver_s6/ipcore_dir/char_fifo_xmdf.tcl
time4clock2/wave_gen_ver_s6/ipcore_dir/clk_core/clk_core.ucf
time4clock2/wave_gen_ver_s6/ipcore_dir/clk_core/clk_wiz_readme.txt
time4clock2/wave_gen_ver_s6/ipcore_dir/clk_core/example_design/clk_core_exdes.v
time4clock2/wave_gen_ver_s6/ipcore_dir/clk_core/example_design/clk_core_exdes.vhd
time4clock2/wave_gen_ver_s6/ipcore_dir/clk_core/implement/implement.bat
time4clock2/wave_gen_ver_s6/ipcore_dir/clk_core/implement/implement.sh
time4clock2/wave_gen_ver_s6/ipcore_dir/clk_core/implement/planAhead_ise.bat
time4clock2/wave_gen_ver_s6/ipcore_dir/clk_core/implement/planAhead_ise.sh
time4clock2/wave_gen_ver_s6/ipcore_dir/clk_core/implement/planAhead_ise.tcl
time4clock2/wave_gen_ver_s6/ipcore_dir/clk_core/implement/xst.prj
time4clock2/wave_gen_ver_s6/ipcore_dir/clk_core/implement/xst.scr
time4clock2/wave_gen_ver_s6/ipcore_dir/clk_core/simulation/clk_core_tb.v
time4clock2/wave_gen_ver_s6/ipcore_dir/clk_core/simulation/clk_core_tb.vhd
time4clock2/wave_gen_ver_s6/ipcore_dir/clk_core/simulation/functional/simcmds.tcl
time4clock2/wave_gen_ver_s6/ipcore_dir/clk_core/simulation/functional/simulate_isim.bat
time4clock2/wave_gen_ver_s6/ipcore_dir/clk_core/simulation/functional/simulate_isim.sh
time4clock2/wave_gen_ver_s6/ipcore_dir/clk_core/simulation/functional/simulate_mti.do
time4clock2/wave_gen_ver_s6/ipcore_dir/clk_core/simulation/functional/simulate_ncsim.sh
time4clock2/wave_gen_ver_s6/ipcore_dir/clk_core/simulation/functional/simulate_vcs.sh
time4clock2/wave_gen_ver_s6/ipcore_dir/clk_core/simulation/functional/ucli_commands.key
time4clock2/wave_gen_ver_s6/ipcore_dir/clk_core/simulation/

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