文件名称:adis16350_all
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This document outlines how to use the Analog Device ADIS16350 High Precision Tri-Axis Inertial Sensor Evaluation Board with the LabVIEW FPGA implementation of the SPI (Serial Peripheral Interface) digital communication protocol. This example reads and displays graphically the acceleration, angular rate and temperature along three axis
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下载文件列表
ADIS16350_All/
ADIS16350_All/ADI16350 RT with FPGA Example/
ADIS16350_All/ADI16350 RT with FPGA Example/ADIS16350/
ADIS16350_All/ADI16350 RT with FPGA Example/ADIS16350/ADIS16350_configuration.vi
ADIS16350_All/ADI16350 RT with FPGA Example/ADIS16350/ADIS16350_convert_bin_to_real.vi
ADIS16350_All/ADI16350 RT with FPGA Example/ADIS16350/ADIS16350_read_pipeline.vi
ADIS16350_All/ADI16350 RT with FPGA Example/ADIS16350/ADIS16350_read_write_single_point.vi
ADIS16350_All/ADI16350 RT with FPGA Example/ADIS16350/ADIS16350_sign_extend_16.vi
ADIS16350_All/ADI16350 RT with FPGA Example/cRIO_ADIS16350_Example.aliases
ADIS16350_All/ADI16350 RT with FPGA Example/cRIO_ADIS16350_Example.lvlps
ADIS16350_All/ADI16350 RT with FPGA Example/cRIO_ADIS16350_Example.lvproj
ADIS16350_All/ADI16350 RT with FPGA Example/Example_cRIO_Host.vi
ADIS16350_All/ADI16350 RT with FPGA Example/Example_cRIO_Main.vi
ADIS16350_All/ADI16350 RT with FPGA Example/Example_Port Code_cRIO.vi
ADIS16350_All/ADI16350 RT with FPGA Example/FPGA Bitfiles/
ADIS16350_All/ADI16350 RT with FPGA Example/FPGA Bitfiles/cRIO_ADIS16003_Exa~3C_FPGA Target_Example_cRIO_Main.vi.lvbit
ADIS16350_All/ADI16350 RT with FPGA Example/FPGA Bitfiles/cRIO_adis16060_Exa~3C_FPGA Target_Example_cRIO_Main.vi.lvbit
ADIS16350_All/ADI16350 RT with FPGA Example/FPGA Bitfiles/cRIO_ADIS16250_Exa~3C_FPGA Target_Example_cRIO_Main.vi.lvbit
ADIS16350_All/ADI16350 RT with FPGA Example/FPGA Bitfiles/cRIO_ADIS16350_Exa~3C_FPGA Target_Example_cRIO_Main.vi.lvbit
ADIS16350_All/FPGA/
ADIS16350_All/FPGA/Code/
ADIS16350_All/FPGA/Code/FPGA SPI_Globals.vi
ADIS16350_All/FPGA/Controls/
ADIS16350_All/FPGA/Controls/FPGA SPI_Arb Loop State.ctl
ADIS16350_All/FPGA/Controls/FPGA SPI_Cmd.ctl
ADIS16350_All/FPGA/Controls/FPGA SPI_Port Loop State.ctl
ADIS16350_All/FPGA/Controls/FPGA SPI_SPI Loop State.ctl
ADIS16350_All/Host API/
ADIS16350_All/Host API/Controls/
ADIS16350_All/Host API/Controls/FPGA SPI_FPGA Ref.ctl
ADIS16350_All/Host API/Controls/FPGA SPI_SPI Configuration Cluster.ctl
ADIS16350_All/Host API/FPGA SPI_Configure.vi
ADIS16350_All/Host API/FPGA SPI_Write Read.vi
ADIS16350_All/Host API/FPGA_Ready.vi
ADIS16350_All/ADI16350 RT with FPGA Example/
ADIS16350_All/ADI16350 RT with FPGA Example/ADIS16350/
ADIS16350_All/ADI16350 RT with FPGA Example/ADIS16350/ADIS16350_configuration.vi
ADIS16350_All/ADI16350 RT with FPGA Example/ADIS16350/ADIS16350_convert_bin_to_real.vi
ADIS16350_All/ADI16350 RT with FPGA Example/ADIS16350/ADIS16350_read_pipeline.vi
ADIS16350_All/ADI16350 RT with FPGA Example/ADIS16350/ADIS16350_read_write_single_point.vi
ADIS16350_All/ADI16350 RT with FPGA Example/ADIS16350/ADIS16350_sign_extend_16.vi
ADIS16350_All/ADI16350 RT with FPGA Example/cRIO_ADIS16350_Example.aliases
ADIS16350_All/ADI16350 RT with FPGA Example/cRIO_ADIS16350_Example.lvlps
ADIS16350_All/ADI16350 RT with FPGA Example/cRIO_ADIS16350_Example.lvproj
ADIS16350_All/ADI16350 RT with FPGA Example/Example_cRIO_Host.vi
ADIS16350_All/ADI16350 RT with FPGA Example/Example_cRIO_Main.vi
ADIS16350_All/ADI16350 RT with FPGA Example/Example_Port Code_cRIO.vi
ADIS16350_All/ADI16350 RT with FPGA Example/FPGA Bitfiles/
ADIS16350_All/ADI16350 RT with FPGA Example/FPGA Bitfiles/cRIO_ADIS16003_Exa~3C_FPGA Target_Example_cRIO_Main.vi.lvbit
ADIS16350_All/ADI16350 RT with FPGA Example/FPGA Bitfiles/cRIO_adis16060_Exa~3C_FPGA Target_Example_cRIO_Main.vi.lvbit
ADIS16350_All/ADI16350 RT with FPGA Example/FPGA Bitfiles/cRIO_ADIS16250_Exa~3C_FPGA Target_Example_cRIO_Main.vi.lvbit
ADIS16350_All/ADI16350 RT with FPGA Example/FPGA Bitfiles/cRIO_ADIS16350_Exa~3C_FPGA Target_Example_cRIO_Main.vi.lvbit
ADIS16350_All/FPGA/
ADIS16350_All/FPGA/Code/
ADIS16350_All/FPGA/Code/FPGA SPI_Globals.vi
ADIS16350_All/FPGA/Controls/
ADIS16350_All/FPGA/Controls/FPGA SPI_Arb Loop State.ctl
ADIS16350_All/FPGA/Controls/FPGA SPI_Cmd.ctl
ADIS16350_All/FPGA/Controls/FPGA SPI_Port Loop State.ctl
ADIS16350_All/FPGA/Controls/FPGA SPI_SPI Loop State.ctl
ADIS16350_All/Host API/
ADIS16350_All/Host API/Controls/
ADIS16350_All/Host API/Controls/FPGA SPI_FPGA Ref.ctl
ADIS16350_All/Host API/Controls/FPGA SPI_SPI Configuration Cluster.ctl
ADIS16350_All/Host API/FPGA SPI_Configure.vi
ADIS16350_All/Host API/FPGA SPI_Write Read.vi
ADIS16350_All/Host API/FPGA_Ready.vi
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