资源列表
EM78P153S-simp
- EM78P153S中文手册，是繁体的，找不到简体版的，这个也一样看。
Verilog_HDL
- Verilog HDL程序设计教程，非常实用，对学习Verilog非常有用。
Verilog_program
- Verilog语法手册，7件逻辑的实现与实验练习，非常实用，对学习Verilog编程很有帮助。
choosedevice
- 文中给出了在数字系统设计时常用的器件,和它们的参数希望对大家有所帮助
failure
- This paper addresses a stochastic-#ow network in which each arc or node has several capacities and may fail. Given the demand d, we try to evaluate the system reliability that the maximum #ow of the network is not less than d. A simple algorithm
constraint
- This paper addresses a stochastic-#ow network in which each arc or node has several capacities and may fail. Given the demand d, we try to evaluate the system reliability that the maximum #ow of the network is not less than d. A simple algorithm
budget
- This paper addresses a stochastic-#ow network in which each arc or node has several capacities and may fail. Given the demand d, we try to evaluate the system reliability that the maximum #ow of the network is not less than d. A simple algorithm
unreliable
- This paper addresses a stochastic-#ow network in which each arc or node has several capacities and may fail. Given the demand d, we try to evaluate the system reliability that the maximum #ow of the network is not less than d. A simple algorithm
Improving
- Each arc of a binary-state network has good/bad states. The system reliability, the probability that source s communicates with sink t, can be computed in terms of minimal paths (MPs). An MP is an ordered sequence of arcs from s to t that has no
CPLDdesign
- 文中给出了使用cpld设计数字系统的完全过程,希望对初学者有所帮助
VHDL21
- 这篇文章给出了一些使用cpld的一些常用程序,希望对大家有用
ClosedLoopPosition
- 转角线位移式全闭环位置伺服系统及误差分析