资源列表
.reg文件全攻略.zip
- .reg文件全攻略
lab11
- computer control_estimators
FIFO
- FIFO(first in first out) design written in Verilog
vad
- voice activity detection
valve.c
- 于勇书上动网格的代码，用来实现一个活塞的运动控制。-yu yong shu shang de dong wang ge de dai ma
2
- Verilog Code By sivanantham and sakthivel Lab assignment-xor gate Do not forget to thank
cong1
- A， 单发单收，在发送状态，能够连续发送从0到99的数字； B， 单发单收，在接收状态，能够接收数据，并在数码管上正确地显示出来； C， 单发多收，在AB完成的基础上，接上多个接收设备，能够正确发送和接收 这 是从站1的main函数代码-A, single-input single in the sending state, capable of continuously transmitting a number from 0 to 99 B, single-input sin
Intro_to_characters
- This intro to characters and it is for educational use only. Only for personal study.-This is intro to characters and it is for educational use only. Only for personal study.
Digital-display
- 51单片机数码管3、8译码器位选动态显示程序-51 single-chip digital decoder bit option 3,8 dynamic display program
SDcard
- sd card initialization and control registers
socket-accept
- Socket下的accept使用说明及介绍 -Socket accept
Hamiltonian_cycle
- Hamiltonian cycle program in JAVA