文件名称:modeldiv5
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- 上传时间：2012-11-16
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文件大小：30.68kb
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无分频电路，实现电路的五分频verilog代码，通过modelsim的仿真-No divider circuit circuit fifth frequency verilog code through modelsim simulation
(系统自动生成,下载前可以参看下载内容)
下载文件列表
modeldiv5/
modeldiv5/div5.cr.mti
modeldiv5/div5.mpf
modeldiv5/div_5.v
modeldiv5/div_5.v.bak
modeldiv5/testdiv.v
modeldiv5/vsim.wlf
modeldiv5/work/
modeldiv5/work/_info
modeldiv5/work/_temp/
modeldiv5/work/_vmake
modeldiv5/work/div_5/
modeldiv5/work/div_5/_primary.dat
modeldiv5/work/div_5/_primary.dbs
modeldiv5/work/div_5/_primary.vhd
modeldiv5/work/div_5/verilog.asm
modeldiv5/work/div_5/verilog.rw
modeldiv5/work/testdiv/
modeldiv5/work/testdiv/_primary.dat
modeldiv5/work/testdiv/_primary.dbs
modeldiv5/work/testdiv/_primary.vhd
modeldiv5/work/testdiv/verilog.asm
modeldiv5/work/testdiv/verilog.rw
modeldiv5/div5.cr.mti
modeldiv5/div5.mpf
modeldiv5/div_5.v
modeldiv5/div_5.v.bak
modeldiv5/testdiv.v
modeldiv5/vsim.wlf
modeldiv5/work/
modeldiv5/work/_info
modeldiv5/work/_temp/
modeldiv5/work/_vmake
modeldiv5/work/div_5/
modeldiv5/work/div_5/_primary.dat
modeldiv5/work/div_5/_primary.dbs
modeldiv5/work/div_5/_primary.vhd
modeldiv5/work/div_5/verilog.asm
modeldiv5/work/div_5/verilog.rw
modeldiv5/work/testdiv/
modeldiv5/work/testdiv/_primary.dat
modeldiv5/work/testdiv/_primary.dbs
modeldiv5/work/testdiv/_primary.vhd
modeldiv5/work/testdiv/verilog.asm
modeldiv5/work/testdiv/verilog.rw
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