资源列表
JIANYISHIZHONG
- 基于FPGA的简易时钟，使用VHDL语言编写。有源代码 可用试验箱实现功能(Simple clock based on FPGA)
97CO011D
- solutions des exercices
RTD2662_Sch
- Schematics for Realtek RTD2662. LCD Driver controller.
Realterm_2.0.0.70_Signed_Wrapper_setup
- arduino terminal rx tx send recive
20170713173850520
- 基于校园的二手物品交易网站的源码 可以用来作为新手学习参考(Source code for second-hand goods trading website based on campus)
PassGuard安全控件技术白皮书
- 密码卫士安全控件技术分析，系统设计，模块设计(Security control technology analysis, system design, module design for password guard)
NOIP2016复赛数据
- 2016年信息学奥林匹克联赛的测试数据，评测用(Test data of the 2016 informatics Olympic League)
hexin_Titleblock -单件图
- CATIA使用宏自动绘制公司或者规定的图框(The use of macro automatic drawing frame)
24种设计模式介绍与6大设计原则
- 设计模式介绍，很实用，值得欣赏，希望大家可以有用(Design pattern introduction, very practical)
IDL源码实现
- 实现NDVI的计算、HANTS滤波算法的NDVI数据平滑和腌摸处理(realize NDVI and hants and NDVI smoothing)
mppt
- this is model matlab simulink tu determine the maximum power point tracking
LLC半桥设计文档
- 该文档详细讲解了LLC半桥电路的设计过程(The document explains the design process of the LLC half bridge circuit in detail.)