资源列表
LowPowerTechniques
- Low Power Design Nano‐scale designs at 130nm and below are now confronted with a power dissipation level beyond the limits of IC packaging and cooling techniques • Consequently in many designs it is not possible to increase the clock speed
physicalDesign
- IL2200ASIC Design Physical Implementation Styles ASIC Design Flow Floor and Power planning Placement Clock Tree Synthesis Routing Timing Analysis Verification and Ener
PLC-note
- PLC note Design and Implementation of A DSSSBased Narrow Band Power Line Communication Modem
RTL-coding-guidelines
- RTL coding guidelines Offer a collection of coding rules and guidelines. Make HDL Codes readable, modifiable, and reusable. Achieve optimal results in synthesis and simulation.
tutorial_asic_v12_1
- tutorial_asic_v12_1 Digital Design Flow Tutorial for EDA Tools: Synopsys Design Compiler Mentor Modelsim Cadence SOC Encounter
verilog_intro-Cygwin
- verilog_intro-Cygwin environment and as a design tool. The Cadence design tool suite is installed on the Linux servers on our network. We will use be using the GUI interface which will allow us to view waveforms in a timing diagram. This also r
2
- Volume issue 2013 [doi 10.1145_2513228.2513294] K. Han J. H. Lim E. G. Im -- Malware analysis method using visualization of binary files.pdf- Volume issue 2013 [doi 10.1145_2513228.2513294] K. Han J. H. Lim E. G. Im -- Malware analysis method usin
Comparison-of-in-memory-dbs
- comparison of nosql databases
ieee
- VLSI Implementation IEEE Papers 2010 to 2014
Text-Clustering-Doc
- Text Document Clustering Document for the MCA and Mtech Students for the final year projects.This Document Clustering is based on several algorithms and full document is presented here.
pcb-designer-use
- pcb designer use 是PCB 设计者需要使用参考的一个很好的规则使用。-pcb designer use，shi pcb she ji zhe xuyao shi yong can kao de yi ge he nhao degui ze shi yong
TechEd2012_DBI-300-7_YingdaDeng
- TechEd2012 sharepoin2013会议资料-TechEd2012 sharepoin2013