资源列表
51code
- 51汇编编程，实现定时T0工作于方式0，通过LED观察现象-51 assembler programming, to achieve timing 0 T0 work in way, LED by observed phenomenon
Stephen
- O Universo numa casca de noz
the-simplex-_-half-duplex-_
- 讲解单工_半双工_全双工的含义及区别，对理解C++有重要帮助-The meaning and the difference on the simplex _ half duplex _ full duplex, is important for understanding the C++
SIM_sim
- sim卡与手机之间通信的apdu.希望对大家能有帮助-this is the apdus for SIM and ME
PCA_FACE_REC
- pca人脸识别代码，亲测可行，且附有图片-pca face recognition code, pro-test feasible and accompanied by pictures
digital-filters
- 数字滤波器,仿真成功为低通滤波器.一个典型的滤波器的仿真 比较详细 还有图-digital filters, the success of the simulation low-pass filter. A typical simulation of the filter there are also more detailed
ISO7816-1234.PDF
- ISO7816中文版，包含1234文档的内容，推荐对照英文文档阅读。-ISO 7816 document
signal_procesing2014
- 数字信号处理基于matlab 文件内容 /conv(卷积部分) dupconv 重叠保留法 freqcirconv 频域圆周卷积 freqconv 频域卷积 timecirconv 时域圆周卷积 timeconv 时域卷积 /fft(频域分析部分) d2fft 基2FFT dft DFT最简化程序 dtft DTFT演示 /fir(fir滤波器设计) fir 得到fir滤波器hn getwindow 得到fir滤波器窗函数wn idealfilter 理想滤波器(低通,高通,带通)hdn
Verilog_Timing
- Verilog_HDL_那些事儿_时序篇v2-Verilog_HDL_ those things _ Timing articles v2
Verilog_Modulation
- VerilogHDL那些事儿_建模篇（for DB4CE15）-VerilogHDL those things _ Modeling articles (for DB4CE15)
Verilog
- 夏宇闻数字逻辑设计，非常好的VHDL学习资料，不多说了-Xia Wen digital logic design, VHDL very good learning materials, not much to say
testProject
- 测试程序，测试编码，非常实用，欢迎欢迎。-Test procedures, test coding, very practical.