资源列表
74lvc1g125
- Bus buffer/line driver 3-state-Bus buffer/line driver 3-state
DHCP
- 常见的小型网络中（例如家庭网络和学生宿舍网），网络管理员都是采用手工分配IP地址的方法，而到了中、大型网络，这种方法就不太适用了。在中、大型网络，特别是大型网络中，往往有超过100台的客户机，手动分配IP地址的方法就不太合适了。DHCP（DynamicHostConfigurationProtocol）为我们解决了这一难题. -Common small networks (such as home networking and student dormitory network), networ
http_pro
- 大家都很熟悉HTTP协议的应用，因为每天都在网络上浏览着不少东西，也都知道是HTTP协议是相当简单的。教你用c实现http协议 -Everyone is familiar with the HTTP protocol applications, because every day' s web with a lot of things, but also all know, HTTP protocol is quite simple. Teach you achieve the http
26246-600
- 3rd Generation Partnership Project Technical Specification Group Services and System Aspects Transparent end-to-end packet switched streaming service (PSS) 3GPP SMIL Language Profile (Release 6)
26245-600
- rd Generation Partnership Project Technical Specification Group Services and System Aspects Transparent end-to-end Packet switched Streaming Service (PSS) Timed text format (Release 6)
22233-630
- 3rd Generation Partnership Project Technical Specification Group Services and System Aspects Transparent end-to-end packet-switched streaming service Stage 1 (Release 6
ASN.1EnDecoder
- ASN.1的编解码规则与应用层网络协议开发。-ASN.1 encoding and decoding of the rules and application layer network protocol development.
clusterImg
- image cluster is formed by using the seed points so called it is a image segmentation-image cluster is formed by using the seed points so called it is a image segmentation
Soft_ware-Keil
- 内含C51的入门，使用方法和详细的实例教程-Containing C51 to introduce the use of examples and detailed tutorial
Soft_ware-CRC
- 基于51单片机的CRC算法的C语言实现(文档内含源代码)-Based on 51 MCU CRC algorithm C language implementation (document containing the source code)
multiclock_design
- 对自己的设计的实现方式越了解，对自己的设计的时序要求越了解，对目标器件的资源分布和结构越了解，对EDA工具执行约束的效果越了解，那么对设计的时序约束目标就会越清晰，相应地，设计的时序收敛过程就会更可控。-The design of their implementations more understanding of the design of their timing requirements more understanding of the target device resource d
1191287106529_xilinx
- 对自己的设计的实现方式越了解，对自己的设计的时序要求越了解，对目标器件的资源分布和结构越了解，对EDA工具执行约束的效果越了解，那么对设计的时序约束目标就会越清晰，相应地，设计的时序收敛过程就会更可控。-The design of their implementations more understanding of the design of their timing requirements more understanding of the target device resource d