TLV1544与TMS320VC5402通过串行口连接，此时，A／D转换芯片作为从设备，DSP提供帧同步和输入／输出时钟信号。TLV1544与DSP之间数据交换的时序图如图3所示。







开始时， 为高电平（芯片处于非激活状态），DATA IN和I/OCLK无效，DATAOUT处于高阻状态。当串行接口使CS变低（激活），芯片开始工作，I／OCLK和DATAIN能使DATA OUT不再处于高阻状态。DSP通过I／OCLK引脚提供输入／输出时钟8序列，当由DSP提供的帧同步脉冲到来后，芯片从DATA IN接收4 b通道选择地址，同时从DATAOUT送出的前一次转换的结果，由DSP串行接收。I／OCLK接收DSP送出的输入序列长度为10～16个时钟周期。前4个有效时钟周期，将从DATAIN输入的4 b输入数据装载到输入数据寄存器，选择所需的模拟通道。接下来的6个时钟周期提供模拟输入采样的控制时间。模拟输入的采样在前10个I／O时钟序列后停止。第10个时钟沿（确切的I／O时钟边缘，即上升沿或下降沿，取决于操作的模式选择）将EOC变低，转换开始。

-TLV1544 with TMS320VC5402 through serial port connectivity, at this time, A / D conversion chip as from the equipment, to provide frame synchronization DSP and input / output clock signal. TLV1544 DSP and data exchange between the chronology of the map is shown in figure 3. At the beginning of the margin (in chip-activated), and I DATA IN / OCLK invalid, DATAOUT at high resistance state. When the serial interface CS change low (activator), the chip start work, I / OCLK and DATAIN can DATA OUT is no longer in a state of high resistance. DSP through I / OCLK pin provide input / output clock 8 sequence, When the DSP from the frame synchronization pulse, the chip from the DATA IN receive four channels to choose b address, DATAOUT sent from the same time the previous conversion results from the