抢答定时器输入端为抢中信号，时钟信号和主持人信号。当主持人信号有效（‘0’）时，时钟信号提供计时，抢中有效之后便开始计时。先将48Mhz时钟分频为1hz的时间信号，当抢中信号有效（‘0’）来临时，将时间到信号（sjd）赋值为无效‘1’，并通过1hz时间信号输出时间显示的七段译码信号：经过一个周期，便将倒计时时间减一，并输出对应时间所示的七段译码值。经过5秒（4，3，…..，0）之后，表示时间到，将时间到信号（sjd）赋值为有效（‘0’）。-Responder timer input is grab the signal, the clock signal and the host signal. When the host signal (' 0 ' ), the clock signal timing, grab began after the effective timing. First 48Mhz clock divider for a 1hz The time signal, to grab the signal (' 0 ' ), the time to signal (sjd) assignment is invalid ' 1' , and by the the 1hz time signal output time display seven segment decoded signal: After a cycle, they put a countdown time minus one and seven-segment decoder output shown in the corresponding time values. After 5 seconds (4,3, ....., 0), represents the time, the time signal (SJD) assignment is valid (' 0 ' ).