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文件名称:video_stream_scaler

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    11.21mb
  • 已下载：
    3次
  • 提 供 者：
    高***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

该模块能对视频分辨实时缩放，采用最近邻域和双线性差值算法。该模块可以实时配置输入输出的分辨率、缩放因子，缩放算法类型等参数，也可在编译时采用默认配置。-The Video Stream Scaler (streamScaler) performs resizing of video streams in a low latency manner, resizing with either bilinear or nearest-neighbor modes.The core offers runtime configuration of input and output resolution, scaling factors, and resize type. Data width, color channels and maximum video resolution can be configuredat compile time.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

video_stream_scaler/doc/src/Block Diagram.vsd
video_stream_scaler/doc/src/Video Stream Scaler Specifications.doc
video_stream_scaler/doc/Video Stream Scaler Specifications.pdf
video_stream_scaler/rtl/verilog/scaler.v
video_stream_scaler/sim/rtl_sim/out/output1280x1024to480x384.raw
video_stream_scaler/sim/rtl_sim/out/output1280x1024to640x512.raw
video_stream_scaler/sim/rtl_sim/out/output1280x1024to960x768.raw
video_stream_scaler/sim/rtl_sim/out/output50x40to640x512clipped.raw
video_stream_scaler/sim/rtl_sim/out/output640x512to1280x1024.raw
video_stream_scaler/sim/rtl_sim/out/output640x512to1280x1024_21extra.raw
video_stream_scaler/sim/rtl_sim/out/output640x512to640x512.raw
video_stream_scaler/sim/rtl_sim/scaler.cr.mti
video_stream_scaler/sim/rtl_sim/scaler.mpf
video_stream_scaler/sim/rtl_sim/scaler.v
video_stream_scaler/sim/rtl_sim/scaler_tb.v
video_stream_scaler/sim/rtl_sim/src/input.tif
video_stream_scaler/sim/rtl_sim/src/input1280x1024boxdiag.bmp
video_stream_scaler/sim/rtl_sim/src/input1280x1024boxdiagRGB.raw
video_stream_scaler/sim/rtl_sim/src/input1280x1024RGB.raw
video_stream_scaler/sim/rtl_sim/src/input640x512boxdiag.bmp
video_stream_scaler/sim/rtl_sim/src/input640x512boxdiagRGB.raw
video_stream_scaler/sim/rtl_sim/src/input640x512RGB.raw
video_stream_scaler/sim/rtl_sim/src/input640x512_21extraRGB.raw
video_stream_scaler/sim/rtl_sim/vsim.wlf
video_stream_scaler/sim/rtl_sim/work/ram@dual@port/verilog.asm
video_stream_scaler/sim/rtl_sim/work/ram@dual@port/verilog.rw
video_stream_scaler/sim/rtl_sim/work/ram@dual@port/_primary.dat
video_stream_scaler/sim/rtl_sim/work/ram@dual@port/_primary.dbs
video_stream_scaler/sim/rtl_sim/work/ram@dual@port/_primary.vhd
video_stream_scaler/sim/rtl_sim/work/ram@fifo/verilog.asm
video_stream_scaler/sim/rtl_sim/work/ram@fifo/verilog.rw
video_stream_scaler/sim/rtl_sim/work/ram@fifo/_primary.dat
video_stream_scaler/sim/rtl_sim/work/ram@fifo/_primary.dbs
video_stream_scaler/sim/rtl_sim/work/ram@fifo/_primary.vhd
video_stream_scaler/sim/rtl_sim/work/scaler@test/verilog.asm
video_stream_scaler/sim/rtl_sim/work/scaler@test/verilog.rw
video_stream_scaler/sim/rtl_sim/work/scaler@test/_primary.dat
video_stream_scaler/sim/rtl_sim/work/scaler@test/_primary.dbs
video_stream_scaler/sim/rtl_sim/work/scaler@test/_primary.vhd
video_stream_scaler/sim/rtl_sim/work/scaler@testbench/verilog.asm
video_stream_scaler/sim/rtl_sim/work/scaler@testbench/verilog.rw
video_stream_scaler/sim/rtl_sim/work/scaler@testbench/_primary.dat
video_stream_scaler/sim/rtl_sim/work/scaler@testbench/_primary.dbs
video_stream_scaler/sim/rtl_sim/work/scaler@testbench/_primary.vhd
video_stream_scaler/sim/rtl_sim/work/stream@scaler/verilog.asm
video_stream_scaler/sim/rtl_sim/work/stream@scaler/verilog.rw
video_stream_scaler/sim/rtl_sim/work/stream@scaler/_primary.dat
video_stream_scaler/sim/rtl_sim/work/stream@scaler/_primary.dbs
video_stream_scaler/sim/rtl_sim/work/stream@scaler/_primary.vhd
video_stream_scaler/sim/rtl_sim/work/_info
video_stream_scaler/sim/rtl_sim/work/_temp/vlog3i6qcw
video_stream_scaler/sim/rtl_sim/work/_temp/vlog9xyg7b
video_stream_scaler/sim/rtl_sim/work/_temp/vlogg3009s
video_stream_scaler/sim/rtl_sim/work/_temp/vloggjv0st
video_stream_scaler/sim/rtl_sim/work/_vmake
video_stream_scaler/sim/rtl_sim/work/ram@dual@port
video_stream_scaler/sim/rtl_sim/work/ram@fifo
video_stream_scaler/sim/rtl_sim/work/scaler@test
video_stream_scaler/sim/rtl_sim/work/scaler@testbench
video_stream_scaler/sim/rtl_sim/work/stream@scaler
video_stream_scaler/sim/rtl_sim/work/_temp
video_stream_scaler/sim/rtl_sim/out
video_stream_scaler/sim/rtl_sim/src
video_stream_scaler/sim/rtl_sim/work
video_stream_scaler/doc/src
video_stream_scaler/rtl/verilog
video_stream_scaler/sim/rtl_sim
video_stream_scaler/doc
video_stream_scaler/rtl
video_stream_scaler/sim
video_stream_scaler

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