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文件名称:S6_VGA

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    3.05mb
  • 已下载：
    0次
  • 提 供 者：
    丁****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

1。源文件保存在src目录，QII的工程文件保存在Proj目录；

2。程序实现的功能是在VGA显示器上显示彩色条纹，共8种颜色，

可以使用嵌入式逻辑分析仪观测信号；

3。modelsim仿真文件在proj--simulation--modelsim中-1. The source file is saved in the src directory QII project file is saved in the directory Proj　2. The functionality of the program is displayed on a VGA monitor color stripes, 8 colors, you can use the embedded logic analyzer observed signals　3. the modelsim simulation files in the proj- simulation- modelsim
(系统自动生成,下载前可以参看下载内容)

下载文件列表

S6_VGA/Src/ColorBar.bdf
S6_VGA/Src/ColorBar.bsf
S6_VGA/Src/vga_vl.v
S6_VGA/Proj/cmp_state.ini
S6_VGA/Proj/ColorBar.asm.rpt
S6_VGA/Proj/ColorBar.cdf
S6_VGA/Proj/ColorBar.done
S6_VGA/Proj/ColorBar.eda.rpt
S6_VGA/Proj/ColorBar.fit.eqn
S6_VGA/Proj/ColorBar.fit.rpt
S6_VGA/Proj/ColorBar.fit.summary
S6_VGA/Proj/ColorBar.flow.rpt
S6_VGA/Proj/ColorBar.map.eqn
S6_VGA/Proj/ColorBar.map.rpt
S6_VGA/Proj/ColorBar.map.summary
S6_VGA/Proj/ColorBar.pin
S6_VGA/Proj/ColorBar.pof
S6_VGA/Proj/ColorBar.qpf
S6_VGA/Proj/ColorBar.qsf
S6_VGA/Proj/ColorBar.qws
S6_VGA/Proj/ColorBar.sof
S6_VGA/Proj/ColorBar.tan.rpt
S6_VGA/Proj/ColorBar.tan.summary
S6_VGA/Proj/ColorBar_assignment_defaults.qdf
S6_VGA/Proj/stp1.stp
S6_VGA/Proj/VGA_PLL.bsf
S6_VGA/Proj/VGA_PLL.v
S6_VGA/Proj/VGA_PLL_bb.v
S6_VGA/Proj/vga_vl.bsf
S6_VGA/Proj/simulation/modelsim/ColorBar.vo
S6_VGA/Proj/simulation/modelsim/ColorBar_modelsim.xrf
S6_VGA/Proj/simulation/modelsim/ColorBar_v.sdo
S6_VGA/Proj/simulation/modelsim/cyclone_atoms.v
S6_VGA/Proj/simulation/modelsim/vga_test.cr.mti
S6_VGA/Proj/simulation/modelsim/vga_test.mpf
S6_VGA/Proj/simulation/modelsim/vga_test.v
S6_VGA/Proj/simulation/modelsim/vga_vl.v
S6_VGA/Proj/simulation/modelsim/vsim.wlf
S6_VGA/Proj/simulation/modelsim/wave.do
S6_VGA/Proj/simulation/modelsim/work/_info
S6_VGA/Proj/simulation/modelsim/work/vga_vl/verilog.asm
S6_VGA/Proj/simulation/modelsim/work/vga_vl/_primary.dat
S6_VGA/Proj/simulation/modelsim/work/vga_vl/_primary.vhd
S6_VGA/Proj/simulation/modelsim/work/vga_test/verilog.asm
S6_VGA/Proj/simulation/modelsim/work/vga_test/_primary.dat
S6_VGA/Proj/simulation/modelsim/work/vga_test/_primary.vhd
S6_VGA/Proj/simulation/modelsim/work/cyclone_scale_cntr/verilog.asm
S6_VGA/Proj/simulation/modelsim/work/cyclone_scale_cntr/_primary.dat
S6_VGA/Proj/simulation/modelsim/work/cyclone_scale_cntr/_primary.vhd
S6_VGA/Proj/simulation/modelsim/work/cyclone_routing_wire/verilog.asm
S6_VGA/Proj/simulation/modelsim/work/cyclone_routing_wire/_primary.dat
S6_VGA/Proj/simulation/modelsim/work/cyclone_routing_wire/_primary.vhd
S6_VGA/Proj/simulation/modelsim/work/cyclone_ram_register/verilog.asm
S6_VGA/Proj/simulation/modelsim/work/cyclone_ram_register/_primary.dat
S6_VGA/Proj/simulation/modelsim/work/cyclone_ram_register/_primary.vhd
S6_VGA/Proj/simulation/modelsim/work/cyclone_ram_pulse_generator/verilog.asm
S6_VGA/Proj/simulation/modelsim/work/cyclone_ram_pulse_generator/_primary.dat
S6_VGA/Proj/simulation/modelsim/work/cyclone_ram_pulse_generator/_primary.vhd
S6_VGA/Proj/simulation/modelsim/work/cyclone_ram_block/verilog.asm
S6_VGA/Proj/simulation/modelsim/work/cyclone_ram_block/_primary.dat
S6_VGA/Proj/simulation/modelsim/work/cyclone_ram_block/_primary.vhd
S6_VGA/Proj/simulation/modelsim/work/cyclone_pll_reg/verilog.asm
S6_VGA/Proj/simulation/modelsim/work/cyclone_pll_reg/_primary.dat
S6_VGA/Proj/simulation/modelsim/work/cyclone_pll_reg/_primary.vhd
S6_VGA/Proj/simulation/modelsim/work/cyclone_pll/verilog.asm
S6_VGA/Proj/simulation/modelsim/work/cyclone_pll/_primary.dat
S6_VGA/Proj/simulation/modelsim/work/cyclone_pll/_primary.vhd
S6_VGA/Proj/simulation/modelsim/work/cyclone_n_cntr/verilog.asm
S6_VGA/Proj/simulation/modelsim/work/cyclone_n_cntr/_primary.dat
S6_VGA/Proj/simulation/modelsim/work/cyclone_n_cntr/_primary.vhd
S6_VGA/Proj/simulation/modelsim/work/cyclone_nmux21/verilog.asm
S6_VGA/Proj/simulation/modelsim/work/cyclone_nmux21/_primary.dat
S6_VGA/Proj/simulation/modelsim/work/cyclone_nmux21/_primary.vhd
S6_VGA/Proj/simulation/modelsim/work/cyclone_m_cntr/verilog.asm
S6_VGA/Proj/simulation/modelsim/work/cyclone_m_cntr/_primary.dat
S6_VGA/Proj/simulation/modelsim/work/cyclone_m_cntr/_primary.vhd
S6_VGA/Proj/simulation/modelsim/work/cyclone_mux41/verilog.asm
S6_VGA/Proj/simulation/modelsim/work/cyclone_mux41/_primary.dat
S6_VGA/Proj/simulation/modelsim/work/cyclone_mux41/_primary.vhd
S6_VGA/Proj/simulation/modelsim/work/cyclone_mux21/verilog.asm
S6_VGA/Proj/simulation/modelsim/work/cyclone_mux21/_primary.dat
S6_VGA/Proj/simulation/modelsim/work/cyclone_mux21/_primary.vhd
S6_VGA/Proj/simulation/modelsim/work/cyclone_lcell_register/verilog.asm
S6_VGA/Proj/simulation/modelsim/work/cyclone_lcell_register/_primary.dat
S6_VGA/Proj/simulation/modelsim/work/cyclone_lcell_register/_primary.vhd
S6_VGA/Proj/simulation/modelsim/work/cyclone_lcell/verilog.asm
S6_VGA/Proj/simulation/modelsim/work/cyclone_lcell/_primary.dat
S6_VGA/Proj/simulation/modelsim/work/cyclone_lcell/_primary.vhd
S6_VGA/Proj/simulation/modelsim/work/cyclone_latch/verilog.asm
S6_VGA/Proj/simulation/modelsim/work/cyclone_latch/_primary.dat
S6_VGA/Proj/simulation/modelsim/work/cyclone_latch/_primary.vhd
S6_VGA/Proj/simulation/modelsim/work/cyclone_jtag/verilog.asm
S6_VGA/Proj/simulation/modelsim/work/cyclone_jtag/_primary.dat
S6_VGA/Proj/simulation/modelsim/work/cyclone_jtag/_primary.vhd
S6_VGA/Proj/simulation/modelsim/work/cyclone_io/verilog.asm
S6_VGA/Proj/simulation/modelsim/work/cyclone_io/_primary.dat
S6_VGA/Proj/simulation/modelsim/work/cyclone_io/_primary.vhd
S6_VGA/Proj/simulation/modelsim/work/cyclone_dll/verilog.asm
S6_VGA/Proj/simulation/modelsim/work/cyclone_dll/_

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