xapp635/left_right_io_placement.ppt
xapp635/readme.txt
xapp635/vhdl/
xapp635/vhdl/simulation/
xapp635/vhdl/simulation/tb_top_4_128.vhd
xapp635/vhdl/simulation/tb_top_4_128_slow.vhd
xapp635/vhdl/simulation/top_4_128.do
xapp635/vhdl/simulation/top_4_128_slow.do
xapp635/vhdl/design_files/
xapp635/vhdl/design_files/rx_4_128_left.vhd
xapp635/vhdl/design_files/rx_4_128_right.vhd
xapp635/vhdl/design_files/serdes_4b_4to1.vhd
xapp635/vhdl/design_files/top_4_128_left_rx.vhd
xapp635/vhdl/design_files/top_4_128_left_rx_slow.vhd
xapp635/vhdl/design_files/top_4_128_right_rx.vhd
xapp635/vhdl/design_files/tx_4_128.vhd
xapp635/vhdl/design_files/tx_4_128_slow.vhd
xapp635/vhdl/constraints/
xapp635/vhdl/constraints/top_4_128_left_rx.ucf
xapp635/vhdl/constraints/top_4_128_left_rx_slow.ucf
xapp635/vhdl/constraints/top_4_128_right_rxr.ucf
xapp635/verilog/
xapp635/verilog/simulation/
xapp635/verilog/simulation/tb_top_4_128.v
xapp635/verilog/simulation/tb_top_4_128_slow.v
xapp635/verilog/simulation/top_4_128.do
xapp635/verilog/simulation/top_4_128_slow.do
xapp635/verilog/design_files/
xapp635/verilog/design_files/rx_4_128_left.v
xapp635/verilog/design_files/rx_4_128_right.v
xapp635/verilog/design_files/serdes_4b_4to1.v
xapp635/verilog/design_files/top_4_128_left_rx.v
xapp635/verilog/design_files/top_4_128_left_rx_slow.v
xapp635/verilog/design_files/top_4_128_right_rx.v
xapp635/verilog/design_files/tx_4_128.v
xapp635/verilog/design_files/tx_4_128_slow.v
xapp635/verilog/constraints/
xapp635/verilog/constraints/top_4_128_left_rx.ucf
xapp635/verilog/constraints/top_4_128_left_rx_slow.ucf
xapp635/verilog/constraints/top_4_128_right_rx.ucf
xapp635/