文件名称:design
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- 上传时间:2012-12-18
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文件大小:196.94kb
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I2C总线的fpga实现,完整工程,已验证通过-Fpga implementation of the I2C bus, complete engineering, has been verified through
(系统自动生成,下载前可以参看下载内容)
下载文件列表
design/I2CSlave.prd
design/I2CSlave.prj
design/I2Cslave.v
design/myram.v
design/rev_1/.recordref
design/rev_1/AutoConstraint_I2Cslave.sdc
design/rev_1/AutoConstraint_myRAM.sdc
design/rev_1/I2Cslave.edf
design/rev_1/I2Cslave.fse
design/rev_1/I2Cslave.htm
design/rev_1/I2Cslave.ncf
design/rev_1/I2Cslave.srd
design/rev_1/I2Cslave.srm
design/rev_1/I2Cslave.srr
design/rev_1/I2Cslave.srs
design/rev_1/I2Cslave.tlg
design/rev_1/myram.edf
design/rev_1/myram.fse
design/rev_1/myram.htm
design/rev_1/myram.ncf
design/rev_1/myram.srd
design/rev_1/myram.srm
design/rev_1/myram.srr
design/rev_1/myram.srs
design/rev_1/myram.tlg
design/rev_1/rpt_I2Cslave.areasrr
design/rev_1/rpt_I2Cslave_areasrr.htm
design/rev_1/rpt_myRAM.areasrr
design/rev_1/rpt_myRAM_areasrr.htm
design/rev_1/rpt_slave_top.areasrr
design/rev_1/rpt_slave_top_areasrr.htm
design/rev_1/slave_top.edf
design/rev_1/slave_top.fse
design/rev_1/slave_top.htm
design/rev_1/slave_top.ncf
design/rev_1/slave_top.srd
design/rev_1/slave_top.srm
design/rev_1/slave_top.srr
design/rev_1/slave_top.srs
design/rev_1/slave_top.tlg
design/rev_1/syntmp/I2Cslave.msg
design/rev_1/syntmp/I2Cslave.plg
design/rev_1/syntmp/I2Cslave_flink.htm
design/rev_1/syntmp/I2Cslave_srr.htm
design/rev_1/syntmp/I2Cslave_toc.htm
design/rev_1/syntmp/myram.msg
design/rev_1/syntmp/myram.plg
design/rev_1/syntmp/myram_flink.htm
design/rev_1/syntmp/myram_srr.htm
design/rev_1/syntmp/myram_toc.htm
design/rev_1/syntmp/slave_top.msg
design/rev_1/syntmp/slave_top.plg
design/rev_1/syntmp/slave_top_flink.htm
design/rev_1/syntmp/slave_top_srr.htm
design/rev_1/syntmp/slave_top_toc.htm
design/rev_1/syntmp/timescale_flink.htm
design/rev_1/syntmp/timescale_srr.htm
design/rev_1/syntmp/timescale_toc.htm
design/rev_1/timescale.htm
design/rev_1/timescale.srr
design/rev_1/traplog.tlg
design/rev_1/verif/I2Cslave.vif
design/rev_1/verif/myram.vif
design/rev_1/verif/slave_top.vif
design/sim/all.do
design/sim/i2c_master_bit_ctrl.v
design/sim/i2c_master_byte_ctrl.v
design/sim/i2c_master_defines.v
design/sim/i2c_master_top.v
design/sim/Sim_Behav.bat
design/sim/timescale.v
design/sim/transcript
design/sim/tst_bench_top.v
design/sim/vish_stacktrace.vstf
design/sim/vsim.wlf
design/sim/wb_master_model.v
design/sim/work/@i2@cslave/verilog.asm
design/sim/work/@i2@cslave/_primary.dat
design/sim/work/@i2@cslave/_primary.vhd
design/sim/work/i2c_master_bit_ctrl/verilog.asm
design/sim/work/i2c_master_bit_ctrl/_primary.dat
design/sim/work/i2c_master_bit_ctrl/_primary.vhd
design/sim/work/i2c_master_byte_ctrl/verilog.asm
design/sim/work/i2c_master_byte_ctrl/_primary.dat
design/sim/work/i2c_master_byte_ctrl/_primary.vhd
design/sim/work/i2c_master_top/verilog.asm
design/sim/work/i2c_master_top/_primary.dat
design/sim/work/i2c_master_top/_primary.vhd
design/sim/work/my@r@a@m/verilog.asm
design/sim/work/my@r@a@m/_primary.dat
design/sim/work/my@r@a@m/_primary.vhd
design/sim/work/tst_bench_top/verilog.asm
design/sim/work/tst_bench_top/_primary.dat
design/sim/work/tst_bench_top/_primary.vhd
design/sim/work/wb_master_model/verilog.asm
design/sim/work/wb_master_model/_primary.dat
design/sim/work/wb_master_model/_primary.vhd
design/sim/work/_info
design/syntmp.msg
design/test.prd
design/test.prj
design/sim/work/@i2@cslave
design/sim/work/i2c_master_bit_ctrl
design/sim/work/i2c_master_byte_ctrl
design/sim/work/i2c_master_top
design/sim/work/my@r@a@m
design/sim/work/tst_bench_top
design/sim/work/wb_master_model
design/rev_1/syntmp
design/rev_1/verif
design/sim/work
design/rev_1
design/sim
design
design/I2CSlave.prj
design/I2Cslave.v
design/myram.v
design/rev_1/.recordref
design/rev_1/AutoConstraint_I2Cslave.sdc
design/rev_1/AutoConstraint_myRAM.sdc
design/rev_1/I2Cslave.edf
design/rev_1/I2Cslave.fse
design/rev_1/I2Cslave.htm
design/rev_1/I2Cslave.ncf
design/rev_1/I2Cslave.srd
design/rev_1/I2Cslave.srm
design/rev_1/I2Cslave.srr
design/rev_1/I2Cslave.srs
design/rev_1/I2Cslave.tlg
design/rev_1/myram.edf
design/rev_1/myram.fse
design/rev_1/myram.htm
design/rev_1/myram.ncf
design/rev_1/myram.srd
design/rev_1/myram.srm
design/rev_1/myram.srr
design/rev_1/myram.srs
design/rev_1/myram.tlg
design/rev_1/rpt_I2Cslave.areasrr
design/rev_1/rpt_I2Cslave_areasrr.htm
design/rev_1/rpt_myRAM.areasrr
design/rev_1/rpt_myRAM_areasrr.htm
design/rev_1/rpt_slave_top.areasrr
design/rev_1/rpt_slave_top_areasrr.htm
design/rev_1/slave_top.edf
design/rev_1/slave_top.fse
design/rev_1/slave_top.htm
design/rev_1/slave_top.ncf
design/rev_1/slave_top.srd
design/rev_1/slave_top.srm
design/rev_1/slave_top.srr
design/rev_1/slave_top.srs
design/rev_1/slave_top.tlg
design/rev_1/syntmp/I2Cslave.msg
design/rev_1/syntmp/I2Cslave.plg
design/rev_1/syntmp/I2Cslave_flink.htm
design/rev_1/syntmp/I2Cslave_srr.htm
design/rev_1/syntmp/I2Cslave_toc.htm
design/rev_1/syntmp/myram.msg
design/rev_1/syntmp/myram.plg
design/rev_1/syntmp/myram_flink.htm
design/rev_1/syntmp/myram_srr.htm
design/rev_1/syntmp/myram_toc.htm
design/rev_1/syntmp/slave_top.msg
design/rev_1/syntmp/slave_top.plg
design/rev_1/syntmp/slave_top_flink.htm
design/rev_1/syntmp/slave_top_srr.htm
design/rev_1/syntmp/slave_top_toc.htm
design/rev_1/syntmp/timescale_flink.htm
design/rev_1/syntmp/timescale_srr.htm
design/rev_1/syntmp/timescale_toc.htm
design/rev_1/timescale.htm
design/rev_1/timescale.srr
design/rev_1/traplog.tlg
design/rev_1/verif/I2Cslave.vif
design/rev_1/verif/myram.vif
design/rev_1/verif/slave_top.vif
design/sim/all.do
design/sim/i2c_master_bit_ctrl.v
design/sim/i2c_master_byte_ctrl.v
design/sim/i2c_master_defines.v
design/sim/i2c_master_top.v
design/sim/Sim_Behav.bat
design/sim/timescale.v
design/sim/transcript
design/sim/tst_bench_top.v
design/sim/vish_stacktrace.vstf
design/sim/vsim.wlf
design/sim/wb_master_model.v
design/sim/work/@i2@cslave/verilog.asm
design/sim/work/@i2@cslave/_primary.dat
design/sim/work/@i2@cslave/_primary.vhd
design/sim/work/i2c_master_bit_ctrl/verilog.asm
design/sim/work/i2c_master_bit_ctrl/_primary.dat
design/sim/work/i2c_master_bit_ctrl/_primary.vhd
design/sim/work/i2c_master_byte_ctrl/verilog.asm
design/sim/work/i2c_master_byte_ctrl/_primary.dat
design/sim/work/i2c_master_byte_ctrl/_primary.vhd
design/sim/work/i2c_master_top/verilog.asm
design/sim/work/i2c_master_top/_primary.dat
design/sim/work/i2c_master_top/_primary.vhd
design/sim/work/my@r@a@m/verilog.asm
design/sim/work/my@r@a@m/_primary.dat
design/sim/work/my@r@a@m/_primary.vhd
design/sim/work/tst_bench_top/verilog.asm
design/sim/work/tst_bench_top/_primary.dat
design/sim/work/tst_bench_top/_primary.vhd
design/sim/work/wb_master_model/verilog.asm
design/sim/work/wb_master_model/_primary.dat
design/sim/work/wb_master_model/_primary.vhd
design/sim/work/_info
design/syntmp.msg
design/test.prd
design/test.prj
design/sim/work/@i2@cslave
design/sim/work/i2c_master_bit_ctrl
design/sim/work/i2c_master_byte_ctrl
design/sim/work/i2c_master_top
design/sim/work/my@r@a@m
design/sim/work/tst_bench_top
design/sim/work/wb_master_model
design/rev_1/syntmp
design/rev_1/verif
design/sim/work
design/rev_1
design/sim
design
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