文件名称:SMBus_Controller
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- 上传时间:2013-01-01
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文件大小:1.66mb
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基于MAX系列CPLD的SMBUS控制器工程文件。代码为VHDL代码-The the SMBUS controller works based on the MAX series CPLDs file. Code for VHDL code
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下载文件列表
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/code/arbitration.v
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/code/bus_idle_detect.v
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/code/mod__crc.v
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/code/op_stage.v
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/code/oscillator.v
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/code/smbus_controller.v
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/arbitration.v
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/bus_idle_detect.v
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/mod__crc.v
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/op_stage.v
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/oscillator.v
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/smbus_controller.cr.mti
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/smbus_controller.mpf
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/smbus_controller.v
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/transcript
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/tst_bnch.v
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/vsim.wlf
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/wave.bmp
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/wave.do
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/arbitration/verilog.psm
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/arbitration/_primary.dat
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/arbitration/_primary.vhd
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/bus_idle_detect/verilog.psm
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/bus_idle_detect/_primary.dat
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/bus_idle_detect/_primary.vhd
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/clkgen_low_extend_detect/verilog.psm
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/clkgen_low_extend_detect/_primary.dat
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/clkgen_low_extend_detect/_primary.vhd
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/fsm/verilog.psm
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/fsm/_primary.dat
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/fsm/_primary.vhd
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/mod_crc/verilog.psm
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/mod_crc/_primary.dat
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/mod_crc/_primary.vhd
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/oscillator/verilog.psm
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/oscillator/_primary.dat
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/oscillator/_primary.vhd
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/oscillator_altufm_osc_7p3/verilog.psm
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/oscillator_altufm_osc_7p3/_primary.dat
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/oscillator_altufm_osc_7p3/_primary.vhd
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/output_stage/verilog.psm
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/output_stage/_primary.dat
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/output_stage/_primary.vhd
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/pec/verilog.psm
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/pec/_primary.dat
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/pec/_primary.vhd
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/piso/verilog.psm
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/piso/_primary.dat
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/piso/_primary.vhd
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/smbus_controller/verilog.psm
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/smbus_controller/_primary.dat
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/smbus_controller/_primary.vhd
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/test_bench/verilog.psm
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/test_bench/_primary.dat
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/test_bench/_primary.vhd
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/_info
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/arbitration.v
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/bus_idle_detect.v
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.(0).cnf.cdb
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.(0).cnf.hdb
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.(1).c
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/code/bus_idle_detect.v
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/code/mod__crc.v
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/code/op_stage.v
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/code/oscillator.v
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/code/smbus_controller.v
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/arbitration.v
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/bus_idle_detect.v
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/mod__crc.v
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/op_stage.v
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/oscillator.v
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/smbus_controller.cr.mti
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/smbus_controller.mpf
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/smbus_controller.v
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/transcript
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/tst_bnch.v
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/vsim.wlf
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/wave.bmp
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/wave.do
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/arbitration/verilog.psm
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/arbitration/_primary.dat
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/arbitration/_primary.vhd
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/bus_idle_detect/verilog.psm
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/bus_idle_detect/_primary.dat
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/bus_idle_detect/_primary.vhd
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/clkgen_low_extend_detect/verilog.psm
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/clkgen_low_extend_detect/_primary.dat
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/clkgen_low_extend_detect/_primary.vhd
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/fsm/verilog.psm
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/fsm/_primary.dat
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/fsm/_primary.vhd
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/mod_crc/verilog.psm
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/mod_crc/_primary.dat
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/mod_crc/_primary.vhd
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/oscillator/verilog.psm
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/oscillator/_primary.dat
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/oscillator/_primary.vhd
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/oscillator_altufm_osc_7p3/verilog.psm
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/oscillator_altufm_osc_7p3/_primary.dat
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/oscillator_altufm_osc_7p3/_primary.vhd
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/output_stage/verilog.psm
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/output_stage/_primary.dat
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/output_stage/_primary.vhd
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/pec/verilog.psm
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/pec/_primary.dat
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/pec/_primary.vhd
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/piso/verilog.psm
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/piso/_primary.dat
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/piso/_primary.vhd
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/smbus_controller/verilog.psm
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/smbus_controller/_primary.dat
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/smbus_controller/_primary.vhd
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/test_bench/verilog.psm
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/test_bench/_primary.dat
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/test_bench/_primary.vhd
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/modelsim/work/_info
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/arbitration.v
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/bus_idle_detect.v
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.(0).cnf.cdb
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.(0).cnf.hdb
SMBus_Controller_Altera_MAX_II_CPLD_Design_Example/quartus/db/smbus_controller.(1).c
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