文件名称:dab1814114c3
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- 上传时间：2013-01-18
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文件大小：859.69kb
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此為採用ALTERA所做的DDR 控制器(verilog)-
File/Directory Descr iption
=============================================================================
\doc DDR SDRAM reference design documentation
\model Contains the verilog SDRAM model
\route Contains the Quartus 2000.05 project files a routed controller design
\simulation Contains the verilog testbench, modelsim project file, and library
\source Contains the verilog source files for the DDR SDRAM reference design
\synthesis\synplicity Contains all synplicity project files associated with synthesizing the reference design
File/Directory Descr iption
=============================================================================
\doc DDR SDRAM reference design documentation
\model Contains the verilog SDRAM model
\route Contains the Quartus 2000.05 project files a routed controller design
\simulation Contains the verilog testbench, modelsim project file, and library
\source Contains the verilog source files for the DDR SDRAM reference design
\synthesis\synplicity Contains all synplicity project files associated with synthesizing the reference design
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下载文件列表
dab1814114c3/
dab1814114c3/doc/
dab1814114c3/doc/ddr_sdram.pdf
dab1814114c3/model/
dab1814114c3/model/mt46v4m16.v
dab1814114c3/readme.txt
dab1814114c3/route/
dab1814114c3/route/ddr_sdram.csf
dab1814114c3/route/ddr_sdram.esf
dab1814114c3/route/ddr_sdram.psf
dab1814114c3/route/ddr_sdram.quartus
dab1814114c3/route/ddr_sdram.vqm
dab1814114c3/route/pll1.v
dab1814114c3/simulation/
dab1814114c3/simulation/ddr_compile_all.v
dab1814114c3/simulation/ddr_sdram_tb.v
dab1814114c3/simulation/modelsim.ini
dab1814114c3/simulation/readme.txt
dab1814114c3/simulation/work/
dab1814114c3/simulation/work/altclklock/
dab1814114c3/simulation/work/altclklock/verilog.psm
dab1814114c3/simulation/work/altclklock/_primary.dat
dab1814114c3/simulation/work/altclklock/_primary.vhd
dab1814114c3/simulation/work/ddr_command/
dab1814114c3/simulation/work/ddr_command/verilog.psm
dab1814114c3/simulation/work/ddr_command/_primary.dat
dab1814114c3/simulation/work/ddr_command/_primary.vhd
dab1814114c3/simulation/work/ddr_control_interface/
dab1814114c3/simulation/work/ddr_control_interface/verilog.psm
dab1814114c3/simulation/work/ddr_control_interface/_primary.dat
dab1814114c3/simulation/work/ddr_control_interface/_primary.vhd
dab1814114c3/simulation/work/ddr_data_path/
dab1814114c3/simulation/work/ddr_data_path/verilog.psm
dab1814114c3/simulation/work/ddr_data_path/_primary.dat
dab1814114c3/simulation/work/ddr_data_path/_primary.vhd
dab1814114c3/simulation/work/ddr_sdram/
dab1814114c3/simulation/work/ddr_sdram/verilog.psm
dab1814114c3/simulation/work/ddr_sdram/_primary.dat
dab1814114c3/simulation/work/ddr_sdram/_primary.vhd
dab1814114c3/simulation/work/ddr_sdram_tb/
dab1814114c3/simulation/work/ddr_sdram_tb/verilog.psm
dab1814114c3/simulation/work/ddr_sdram_tb/_primary.dat
dab1814114c3/simulation/work/ddr_sdram_tb/_primary.vhd
dab1814114c3/simulation/work/mt46v4m16/
dab1814114c3/simulation/work/mt46v4m16/verilog.psm
dab1814114c3/simulation/work/mt46v4m16/_primary.dat
dab1814114c3/simulation/work/mt46v4m16/_primary.vhd
dab1814114c3/simulation/work/pll1/
dab1814114c3/simulation/work/pll1/verilog.psm
dab1814114c3/simulation/work/pll1/_primary.dat
dab1814114c3/simulation/work/pll1/_primary.vhd
dab1814114c3/simulation/work/_info
dab1814114c3/source/
dab1814114c3/source/altclklock.v
dab1814114c3/source/ddr_Command.v
dab1814114c3/source/ddr_control_interface.v
dab1814114c3/source/ddr_data_path.v
dab1814114c3/source/ddr_sdram.v
dab1814114c3/source/Params.v
dab1814114c3/source/pll1.v
dab1814114c3/synthesis/
dab1814114c3/synthesis/synplicity/
dab1814114c3/synthesis/synplicity/ddr_data_path.srm
dab1814114c3/synthesis/synplicity/ddr_data_path.srr
dab1814114c3/synthesis/synplicity/ddr_data_path.srs
dab1814114c3/synthesis/synplicity/ddr_data_path.tlg
dab1814114c3/synthesis/synplicity/ddr_data_path.xrf
dab1814114c3/synthesis/synplicity/ddr_sdram.prj
dab1814114c3/synthesis/synplicity/ddr_sdram.sdc
dab1814114c3/synthesis/synplicity/ddr_sdram.srm
dab1814114c3/synthesis/synplicity/ddr_sdram.srr
dab1814114c3/synthesis/synplicity/ddr_sdram.srs
dab1814114c3/synthesis/synplicity/ddr_sdram.tcl
dab1814114c3/synthesis/synplicity/ddr_sdram.tlg
dab1814114c3/synthesis/synplicity/ddr_sdram.vqm
dab1814114c3/synthesis/synplicity/ddr_sdram.xrf
dab1814114c3/synthesis/synplicity/ddr_sdram_cons.tcl
dab1814114c3/synthesis/synplicity/ddr_sdram_rm.tcl
dab1814114c3/doc/
dab1814114c3/doc/ddr_sdram.pdf
dab1814114c3/model/
dab1814114c3/model/mt46v4m16.v
dab1814114c3/readme.txt
dab1814114c3/route/
dab1814114c3/route/ddr_sdram.csf
dab1814114c3/route/ddr_sdram.esf
dab1814114c3/route/ddr_sdram.psf
dab1814114c3/route/ddr_sdram.quartus
dab1814114c3/route/ddr_sdram.vqm
dab1814114c3/route/pll1.v
dab1814114c3/simulation/
dab1814114c3/simulation/ddr_compile_all.v
dab1814114c3/simulation/ddr_sdram_tb.v
dab1814114c3/simulation/modelsim.ini
dab1814114c3/simulation/readme.txt
dab1814114c3/simulation/work/
dab1814114c3/simulation/work/altclklock/
dab1814114c3/simulation/work/altclklock/verilog.psm
dab1814114c3/simulation/work/altclklock/_primary.dat
dab1814114c3/simulation/work/altclklock/_primary.vhd
dab1814114c3/simulation/work/ddr_command/
dab1814114c3/simulation/work/ddr_command/verilog.psm
dab1814114c3/simulation/work/ddr_command/_primary.dat
dab1814114c3/simulation/work/ddr_command/_primary.vhd
dab1814114c3/simulation/work/ddr_control_interface/
dab1814114c3/simulation/work/ddr_control_interface/verilog.psm
dab1814114c3/simulation/work/ddr_control_interface/_primary.dat
dab1814114c3/simulation/work/ddr_control_interface/_primary.vhd
dab1814114c3/simulation/work/ddr_data_path/
dab1814114c3/simulation/work/ddr_data_path/verilog.psm
dab1814114c3/simulation/work/ddr_data_path/_primary.dat
dab1814114c3/simulation/work/ddr_data_path/_primary.vhd
dab1814114c3/simulation/work/ddr_sdram/
dab1814114c3/simulation/work/ddr_sdram/verilog.psm
dab1814114c3/simulation/work/ddr_sdram/_primary.dat
dab1814114c3/simulation/work/ddr_sdram/_primary.vhd
dab1814114c3/simulation/work/ddr_sdram_tb/
dab1814114c3/simulation/work/ddr_sdram_tb/verilog.psm
dab1814114c3/simulation/work/ddr_sdram_tb/_primary.dat
dab1814114c3/simulation/work/ddr_sdram_tb/_primary.vhd
dab1814114c3/simulation/work/mt46v4m16/
dab1814114c3/simulation/work/mt46v4m16/verilog.psm
dab1814114c3/simulation/work/mt46v4m16/_primary.dat
dab1814114c3/simulation/work/mt46v4m16/_primary.vhd
dab1814114c3/simulation/work/pll1/
dab1814114c3/simulation/work/pll1/verilog.psm
dab1814114c3/simulation/work/pll1/_primary.dat
dab1814114c3/simulation/work/pll1/_primary.vhd
dab1814114c3/simulation/work/_info
dab1814114c3/source/
dab1814114c3/source/altclklock.v
dab1814114c3/source/ddr_Command.v
dab1814114c3/source/ddr_control_interface.v
dab1814114c3/source/ddr_data_path.v
dab1814114c3/source/ddr_sdram.v
dab1814114c3/source/Params.v
dab1814114c3/source/pll1.v
dab1814114c3/synthesis/
dab1814114c3/synthesis/synplicity/
dab1814114c3/synthesis/synplicity/ddr_data_path.srm
dab1814114c3/synthesis/synplicity/ddr_data_path.srr
dab1814114c3/synthesis/synplicity/ddr_data_path.srs
dab1814114c3/synthesis/synplicity/ddr_data_path.tlg
dab1814114c3/synthesis/synplicity/ddr_data_path.xrf
dab1814114c3/synthesis/synplicity/ddr_sdram.prj
dab1814114c3/synthesis/synplicity/ddr_sdram.sdc
dab1814114c3/synthesis/synplicity/ddr_sdram.srm
dab1814114c3/synthesis/synplicity/ddr_sdram.srr
dab1814114c3/synthesis/synplicity/ddr_sdram.srs
dab1814114c3/synthesis/synplicity/ddr_sdram.tcl
dab1814114c3/synthesis/synplicity/ddr_sdram.tlg
dab1814114c3/synthesis/synplicity/ddr_sdram.vqm
dab1814114c3/synthesis/synplicity/ddr_sdram.xrf
dab1814114c3/synthesis/synplicity/ddr_sdram_cons.tcl
dab1814114c3/synthesis/synplicity/ddr_sdram_rm.tcl
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