S6_VGA/
S6_VGA/.sopc_builder/
S6_VGA/.sopc_builder/filters.xml
S6_VGA/Doc/
S6_VGA/Doc/程序说明.txt
S6_VGA/MAC_rx.bsf
S6_VGA/MAC_top.bsf
S6_VGA/Proj/
S6_VGA/Proj/.sopc_builder/
S6_VGA/Proj/.sopc_builder/filters.xml
S6_VGA/Proj/.sopc_builder/preferences.xml
S6_VGA/Proj/ColorBar.asm.rpt
S6_VGA/Proj/ColorBar.cdf
S6_VGA/Proj/ColorBar.done
S6_VGA/Proj/ColorBar.eda.rpt
S6_VGA/Proj/ColorBar.fit.eqn
S6_VGA/Proj/ColorBar.fit.rpt
S6_VGA/Proj/ColorBar.fit.summary
S6_VGA/Proj/ColorBar.flow.rpt
S6_VGA/Proj/ColorBar.map.eqn
S6_VGA/Proj/ColorBar.map.rpt
S6_VGA/Proj/ColorBar.map.summary
S6_VGA/Proj/ColorBar.pin
S6_VGA/Proj/ColorBar.pof
S6_VGA/Proj/ColorBar.qpf
S6_VGA/Proj/ColorBar.qsf
S6_VGA/Proj/ColorBar.sof
S6_VGA/Proj/ColorBar.tan.rpt
S6_VGA/Proj/ColorBar.tan.summary
S6_VGA/Proj/ColorBar_assignment_defaults.qdf
S6_VGA/Proj/VGA_PLL.bsf
S6_VGA/Proj/VGA_PLL.v
S6_VGA/Proj/VGA_PLL_bb.v
S6_VGA/Proj/altpllpll_0.v
S6_VGA/Proj/cmp_state.ini
S6_VGA/Proj/db/
S6_VGA/Proj/db/ColorBar.db_info
S6_VGA/Proj/db/ColorBar.eco.cdb
S6_VGA/Proj/db/ColorBar.sld_design_entry.sci
S6_VGA/Proj/db/ColorBar_cmp.qrpt
S6_VGA/Proj/db/altsyncram_1f92.tdf
S6_VGA/Proj/db/altsyncram_fl82.tdf
S6_VGA/Proj/db/altsyncram_hl82.tdf
S6_VGA/Proj/db/altsyncram_qso3.tdf
S6_VGA/Proj/db/cmpr_j4c.tdf
S6_VGA/Proj/db/cmpr_l4c.tdf
S6_VGA/Proj/db/cmpr_n4c.tdf
S6_VGA/Proj/db/cntr_a4i.tdf
S6_VGA/Proj/db/cntr_cti.tdf
S6_VGA/Proj/db/cntr_f29.tdf
S6_VGA/Proj/db/cntr_gq7.tdf
S6_VGA/Proj/db/cntr_ln7.tdf
S6_VGA/Proj/db/cntr_no8.tdf
S6_VGA/Proj/db/cntr_p2i.tdf
S6_VGA/Proj/db/cntr_qt7.tdf
S6_VGA/Proj/db/cntr_rt7.tdf
S6_VGA/Proj/db/cntr_umi.tdf
S6_VGA/Proj/db/cntr_vt9.tdf
S6_VGA/Proj/db/decode_9ie.tdf
S6_VGA/Proj/db/decode_9jf.tdf
S6_VGA/Proj/db/mux_ngc.tdf
S6_VGA/Proj/db/prev_cmp_ColorBar.map.qmsg
S6_VGA/Proj/db/prev_cmp_ColorBar.qmsg
S6_VGA/Proj/simulation/
S6_VGA/Proj/simulation/modelsim/
S6_VGA/Proj/simulation/modelsim/ColorBar.vo
S6_VGA/Proj/simulation/modelsim/ColorBar_modelsim.xrf
S6_VGA/Proj/simulation/modelsim/ColorBar_v.sdo
S6_VGA/Proj/simulation/modelsim/cyclone_atoms.v
S6_VGA/Proj/simulation/modelsim/vga_test.cr.mti
S6_VGA/Proj/simulation/modelsim/vga_test.mpf
S6_VGA/Proj/simulation/modelsim/vga_test.v
S6_VGA/Proj/simulation/modelsim/vga_vl.v
S6_VGA/Proj/simulation/modelsim/vsim.wlf
S6_VGA/Proj/simulation/modelsim/wave.do
S6_VGA/Proj/simulation/modelsim/work/
S6_VGA/Proj/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e/
S6_VGA/Proj/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e/_primary.dat
S6_VGA/Proj/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e/_primary.vhd
S6_VGA/Proj/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e/verilog.asm
S6_VGA/Proj/simulation/modelsim/work/@color@bar/
S6_VGA/Proj/simulation/modelsim/work/@color@bar/_primary.dat
S6_VGA/Proj/simulation/modelsim/work/@color@bar/_primary.vhd
S6_VGA/Proj/simulation/modelsim/work/@color@bar/verilog.asm
S6_VGA/Proj/simulation/modelsim/work/_info
S6_VGA/Proj/simulation/modelsim/work/cyclone_and1/
S6_VGA/Proj/simulation/modelsim/work/cyclone_and1/_primary.dat
S6_VGA/Proj/simulation/modelsim/work/cyclone_and1/_primary.vhd
S6_VGA/Proj/simulation/modelsim/work/cyclone_and1/verilog.asm
S6_VGA/Proj/simulation/modelsim/work/cyclone_and16/
S6_VGA/Proj/simulation/modelsim/work/cyclone_and16/_primary.dat
S6_VGA/Proj/simulation/modelsim/work/cyclone_and16/_primary.vhd
S6_VGA/Proj/simulation/modelsim/work/cyclone_and16/verilog.asm
S6_VGA/Proj/simulation/modelsim/work/cyclone_asmiblock/
S6_VGA/Proj/simulation/modelsim/work/cyclone_asmiblock/_primary.dat
S6_VGA/Proj/simulation/modelsim/work/cyclone_asmiblock/_primary.vhd
S6_VGA/Proj/simulation/modelsim/work/cyclone_asmiblock/verilog.asm
S6_VGA/Proj/simulation/modelsim/work/cyclone_asynch_io/
S6_VGA/Proj/simulation/modelsim/work/cyclone_asynch_io/_primary.dat
S6_VGA/Proj/simulation/modelsim/work/cyclone_asynch_io/_primary.vhd
S6_VGA/Proj/simulation/modelsim/work/cyclone_asynch_io/verilog.asm
S6_VGA/Proj/simulation/modelsim/work/cyclone_asynch_lcell/
S6_VGA/Proj/simulation/modelsim/work/cyclone_asynch_lcell/_primary.dat
S6_VGA/Proj/simulation/modelsim/work/cyclone_asynch_lcell/_primary.vhd
S6_VGA/Proj/simulation/modelsim/work/cyclone_asynch_lcell/verilog.asm
S6_VGA/Proj/simulation/modelsim/work/cyclone_b17mux21/
S6_VGA/Proj/simulation/modelsim/work/cyclone_b17mux21/_primary.dat
S6_VGA/Proj/simulation/modelsim/work/cyclone_b17mux21/_primary.vhd
S6_VGA/Proj/simulation/modelsim/work/cyclone_b17mux21/verilog.asm
S6_VGA/Proj/simulation/modelsim/work/cyclone_b5mux21/
S6_VGA/Proj/simulation/modelsim/work/cyclone_b5mux21/_primary.dat
S6_VGA/Proj/simulation/modelsim/work/cyclone_b5mux21/_primary.vhd
S6_VGA/Proj/simulation/modelsim/work/cyclone_b5mux21/verilog.asm
S6_VGA/Proj/simulation/modelsim/work/cyclone_bmux21/
S6_VGA/Proj/simulation/modelsim/work/cyclone_bmux21/_primary.dat
S6_VGA/Proj/simulation/modelsim/work/cyclone_bmux21/_primary.vhd
S6_VGA/Proj/simulation/modelsim/work/cyclone_bmux21/verilog.asm
S6_VGA/Proj/simulation/modelsim/work/cyclone_crcblock/
S6_VGA/Proj/simulation/modelsim/work/cyclone_crcblock/_primary.dat
S6_VGA/Proj/simulation/modelsim/work/cyclone_crcbl