本文的初衷是为了使已经对Verilog HDL有过初步了解的读者，能够进一步了解Verilog HDL与综合后的硬件之间的映射关系，从而改善代码风格，写出高效可综合的代码。-The original intention of this article to make readers already have a preliminary understanding of the Verilog HDL, and be able to learn more about the mapping between the Verilog HDL synthesis hardware to improve code style, to write efficient code can be integrated.