final/
final/alu.v
final/clk_gen.v
final/cycloneii_atoms.v
final/dmem.v
final/ID.v
final/IE.v
final/IF.v
final/imem.v
final/MiniRisc_top.v
final/multi_flag_ctrl.v
final/register.v
final/reg_dmem_rw.v
final/risc.cr.mti
final/risc.mpf
final/sign_extend.v
final/test_bench2.v
final/top_module.v
final/vsim.wlf
final/work/
final/work/@a@l@u/
final/work/@a@l@u/verilog.asm
final/work/@a@l@u/_primary.dat
final/work/@a@l@u/_primary.vhd
final/work/@c@y@c@l@o@n@e@i@i_@p@r@i@m_@d@f@f@e/
final/work/@c@y@c@l@o@n@e@i@i_@p@r@i@m_@d@f@f@e/verilog.asm
final/work/@c@y@c@l@o@n@e@i@i_@p@r@i@m_@d@f@f@e/_primary.dat
final/work/@c@y@c@l@o@n@e@i@i_@p@r@i@m_@d@f@f@e/_primary.vhd
final/work/@i@d/
final/work/@i@d/verilog.asm
final/work/@i@d/_primary.dat
final/work/@i@d/_primary.vhd
final/work/@i@e/
final/work/@i@e/verilog.asm
final/work/@i@e/_primary.dat
final/work/@i@e/_primary.vhd
final/work/@i@f/
final/work/@i@f/verilog.asm
final/work/@i@f/_primary.dat
final/work/@i@f/_primary.vhd
final/work/@mini@risc_@c@p@u/
final/work/@mini@risc_@c@p@u/verilog.asm
final/work/@mini@risc_@c@p@u/_primary.dat
final/work/@mini@risc_@c@p@u/_primary.vhd
final/work/@mini@risc_top/
final/work/@mini@risc_top/verilog.asm
final/work/@mini@risc_top/_primary.dat
final/work/@mini@risc_top/_primary.vhd
final/work/clk_gen/
final/work/clk_gen/verilog.asm
final/work/clk_gen/_primary.dat
final/work/clk_gen/_primary.vhd
final/work/cycloneii_and1/
final/work/cycloneii_and16/
final/work/cycloneii_and16/verilog.asm
final/work/cycloneii_and16/_primary.dat
final/work/cycloneii_and16/_primary.vhd
final/work/cycloneii_and1/verilog.asm
final/work/cycloneii_and1/_primary.dat
final/work/cycloneii_and1/_primary.vhd
final/work/cycloneii_asmiblock/
final/work/cycloneii_asmiblock/verilog.asm
final/work/cycloneii_asmiblock/_primary.dat
final/work/cycloneii_asmiblock/_primary.vhd
final/work/cycloneii_asynch_io/
final/work/cycloneii_asynch_io/verilog.asm
final/work/cycloneii_asynch_io/_primary.dat
final/work/cycloneii_asynch_io/_primary.vhd
final/work/cycloneii_b17mux21/
final/work/cycloneii_b17mux21/verilog.asm
final/work/cycloneii_b17mux21/_primary.dat
final/work/cycloneii_b17mux21/_primary.vhd
final/work/cycloneii_b5mux21/
final/work/cycloneii_b5mux21/verilog.asm
final/work/cycloneii_b5mux21/_primary.dat
final/work/cycloneii_b5mux21/_primary.vhd
final/work/cycloneii_bmux21/
final/work/cycloneii_bmux21/verilog.asm
final/work/cycloneii_bmux21/_primary.dat
final/work/cycloneii_bmux21/_primary.vhd
final/work/cycloneii_clkctrl/
final/work/cycloneii_clkctrl/verilog.asm
final/work/cycloneii_clkctrl/_primary.dat
final/work/cycloneii_clkctrl/_primary.vhd
final/work/cycloneii_clk_delay_cal_ctrl/
final/work/cycloneii_clk_delay_cal_ctrl/verilog.asm
final/work/cycloneii_clk_delay_cal_ctrl/_primary.dat
final/work/cycloneii_clk_delay_cal_ctrl/_primary.vhd
final/work/cycloneii_clk_delay_ctrl/
final/work/cycloneii_clk_delay_ctrl/verilog.asm
final/work/cycloneii_clk_delay_ctrl/_primary.dat
final/work/cycloneii_clk_delay_ctrl/_primary.vhd
final/work/cycloneii_crcblock/
final/work/cycloneii_crcblock/verilog.asm
final/work/cycloneii_crcblock/_primary.dat
final/work/cycloneii_crcblock/_primary.vhd
final/work/cycloneii_dffe/
final/work/cycloneii_dffe/verilog.asm
final/work/cycloneii_dffe/_primary.dat
final/work/cycloneii_dffe/_primary.vhd
final/work/cycloneii_ena_reg/
final/work/cycloneii_ena_reg/verilog.asm
final/work/cycloneii_ena_reg/_primary.dat
final/work/cycloneii_ena_reg/_primary.vhd
final/work/cycloneii_io/
final/work/cycloneii_io/verilog.asm
final/work/cycloneii_io/_primary.dat
final/work/cycloneii_io/_primary.vhd
final/work/cycloneii_jtag/
final/work/cycloneii_jtag/verilog.asm
final/work/cycloneii_jtag/_primary.dat
final/work/cycloneii_jtag/_primary.vhd
final/work/cycloneii_latch/
final/work/cycloneii_latch/verilog.asm
final/work/cycloneii_latch/_primary.dat
final/work/cycloneii_latch/_primary.vhd
final/work/cycloneii_lcell_comb/
final/work/cycloneii_lcell_comb/verilog.asm
final/work/cycloneii_lcell_comb/_primary.dat
final/work/cycloneii_lcell_comb/_primary.vhd
final/work/cycloneii_lcell_ff/
final/work/cycloneii_lcell_ff/verilog.asm
final/work/cycloneii_lcell_ff/_primary.dat
final/work/cycloneii_lcell_ff/_primary.vhd
final/work/cycloneii_mac_data_reg/
final/work/cycloneii_mac_data_reg/verilog.asm
final/work/cycloneii_mac_data_reg/_primary.dat
final/work/cycloneii_mac_data_reg/_primary.vhd
final/work/cycloneii_mac_mult/
final/work/cycloneii_mac_mult/verilog.asm
final/work/cycloneii_mac_mult/_primary.dat
final/work/cycloneii_mac_mult/_primary.vhd
final/work/cycloneii_mac_mult_internal/
final/work/cycloneii_mac_mult_internal/verilog.asm
final/work/cycloneii_mac_mult_internal/_primary.dat
final/work/cycloneii_mac_mult_internal/_primary.vhd
final/work/cycloneii_mac_out/
final/work/cycloneii_mac_out/verilog.asm
final/work/cycloneii_mac_out/_primary.dat
final/work/cycloneii_mac_out/_primary.vhd
final/work/cycloneii_mac_sign_reg/
final/work/cycloneii_mac_sign_reg/verilog.asm
final/work/cycloneii_mac_sign_reg/_primary.dat
final/work/cycloneii_mac_sign_reg/_primary.vhd
final/work/cycloneii_mux21/
final/work/cycloneii_mux