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文件名称:i2c-slave

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    2013-03-16
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    290.98kb
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verilog HDL i2c协议从机的编写-verilog i2c protocol from the machine
(系统自动生成,下载前可以参看下载内容)

下载文件列表

I2C/design/I2CSlave.prd
I2C/design/I2CSlave.prj
I2C/design/I2Cslave.v
I2C/design/myram.v
I2C/design/rev_1/.recordref
I2C/design/rev_1/AutoConstraint_I2Cslave.sdc
I2C/design/rev_1/AutoConstraint_myRAM.sdc
I2C/design/rev_1/I2Cslave.edf
I2C/design/rev_1/I2Cslave.fse
I2C/design/rev_1/I2Cslave.htm
I2C/design/rev_1/I2Cslave.ncf
I2C/design/rev_1/I2Cslave.srd
I2C/design/rev_1/I2Cslave.srm
I2C/design/rev_1/I2Cslave.srr
I2C/design/rev_1/I2Cslave.srs
I2C/design/rev_1/I2Cslave.tlg
I2C/design/rev_1/myram.edf
I2C/design/rev_1/myram.fse
I2C/design/rev_1/myram.htm
I2C/design/rev_1/myram.ncf
I2C/design/rev_1/myram.srd
I2C/design/rev_1/myram.srm
I2C/design/rev_1/myram.srr
I2C/design/rev_1/myram.srs
I2C/design/rev_1/myram.tlg
I2C/design/rev_1/rpt_I2Cslave.areasrr
I2C/design/rev_1/rpt_I2Cslave_areasrr.htm
I2C/design/rev_1/rpt_myRAM.areasrr
I2C/design/rev_1/rpt_myRAM_areasrr.htm
I2C/design/rev_1/rpt_slave_top.areasrr
I2C/design/rev_1/rpt_slave_top_areasrr.htm
I2C/design/rev_1/slave_top.edf
I2C/design/rev_1/slave_top.fse
I2C/design/rev_1/slave_top.htm
I2C/design/rev_1/slave_top.ncf
I2C/design/rev_1/slave_top.srd
I2C/design/rev_1/slave_top.srm
I2C/design/rev_1/slave_top.srr
I2C/design/rev_1/slave_top.srs
I2C/design/rev_1/slave_top.tlg
I2C/design/rev_1/syntmp/I2Cslave.msg
I2C/design/rev_1/syntmp/I2Cslave.plg
I2C/design/rev_1/syntmp/I2Cslave_flink.htm
I2C/design/rev_1/syntmp/I2Cslave_srr.htm
I2C/design/rev_1/syntmp/I2Cslave_toc.htm
I2C/design/rev_1/syntmp/myram.msg
I2C/design/rev_1/syntmp/myram.plg
I2C/design/rev_1/syntmp/myram_flink.htm
I2C/design/rev_1/syntmp/myram_srr.htm
I2C/design/rev_1/syntmp/myram_toc.htm
I2C/design/rev_1/syntmp/slave_top.msg
I2C/design/rev_1/syntmp/slave_top.plg
I2C/design/rev_1/syntmp/slave_top_flink.htm
I2C/design/rev_1/syntmp/slave_top_srr.htm
I2C/design/rev_1/syntmp/slave_top_toc.htm
I2C/design/rev_1/syntmp/timescale_flink.htm
I2C/design/rev_1/syntmp/timescale_srr.htm
I2C/design/rev_1/syntmp/timescale_toc.htm
I2C/design/rev_1/syntmp
I2C/design/rev_1/timescale.htm
I2C/design/rev_1/timescale.srr
I2C/design/rev_1/traplog.tlg
I2C/design/rev_1/verif/I2Cslave.vif
I2C/design/rev_1/verif/myram.vif
I2C/design/rev_1/verif/slave_top.vif
I2C/design/rev_1/verif
I2C/design/rev_1
I2C/design/sim/all.do
I2C/design/sim/i2c_master_bit_ctrl.v
I2C/design/sim/i2c_master_byte_ctrl.v
I2C/design/sim/i2c_master_defines.v
I2C/design/sim/i2c_master_top.v
I2C/design/sim/Sim_Behav.bat
I2C/design/sim/timescale.v
I2C/design/sim/transcript
I2C/design/sim/tst_bench_top.v
I2C/design/sim/vish_stacktrace.vstf
I2C/design/sim/vsim.wlf
I2C/design/sim/wb_master_model.v
I2C/design/sim/work/@i2@cslave/verilog.asm
I2C/design/sim/work/@i2@cslave/_primary.dat
I2C/design/sim/work/@i2@cslave/_primary.vhd
I2C/design/sim/work/@i2@cslave
I2C/design/sim/work/i2c_master_bit_ctrl/verilog.asm
I2C/design/sim/work/i2c_master_bit_ctrl/_primary.dat
I2C/design/sim/work/i2c_master_bit_ctrl/_primary.vhd
I2C/design/sim/work/i2c_master_bit_ctrl
I2C/design/sim/work/i2c_master_byte_ctrl/verilog.asm
I2C/design/sim/work/i2c_master_byte_ctrl/_primary.dat
I2C/design/sim/work/i2c_master_byte_ctrl/_primary.vhd
I2C/design/sim/work/i2c_master_byte_ctrl
I2C/design/sim/work/i2c_master_top/verilog.asm
I2C/design/sim/work/i2c_master_top/_primary.dat
I2C/design/sim/work/i2c_master_top/_primary.vhd
I2C/design/sim/work/i2c_master_top
I2C/design/sim/work/my@r@a@m/verilog.asm
I2C/design/sim/work/my@r@a@m/_primary.dat
I2C/design/sim/work/my@r@a@m/_primary.vhd
I2C/design/sim/work/my@r@a@m
I2C/design/sim/work/tst_bench_top/verilog.asm
I2C/design/sim/work/tst_bench_top/_primary.dat
I2C/design/sim/work/tst_bench_top/_primary.vhd
I2C/design/sim/work/tst_bench_top
I2C/design/sim/work/wb_master_model/verilog.asm
I2C/design/sim/work/wb_master_model/_primary.dat
I2C/design/sim/work/wb_master_model/_primary.vhd
I2C/design/sim/work/wb_master_model
I2C/design/sim/work/_info
I2C/design/sim/work
I2C/design/sim
I2C/design/syntmp.msg
I2C/design/test.prd
I2C/design/test.prj
I2C/design
I2C/I2C Slave设计笔记.doc
I2C
I2C/[原创]兼容opencores_org的I2C slave的rtl代码 - 资料共享 - ASIC-FPGA-CPLD 设计(数字前端) - 中国电子顶级开发网 国内最顶级的开发者论坛---FPGAASICDSPARM单片机MCU电子电路嵌入式开发设计 - Powered by Discuz!.mht

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