文件名称:clock1
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- 上传时间:2013-03-16
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文件大小:893.02kb
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自己编写的数字钟,可复位,可加减调小时和分钟,内带引脚配置文件,可以在开发板上运行-Themselves prepared digital clock, reset, can be modified tone in hours and minutes, with a pin configuration file, can be in the development board to run themselves prepared digital clock, reset, can be modified tone in hours and minutes, with a pin configuration file, in the development board operation
(系统自动生成,下载前可以参看下载内容)
下载文件列表
clock1/
clock1/db/
clock1/db/alt_u_div_m0f.tdf
clock1/db/fpga.(0).cnf.cdb
clock1/db/fpga.(0).cnf.hdb
clock1/db/fpga.(1).cnf.cdb
clock1/db/fpga.(1).cnf.hdb
clock1/db/fpga.(10).cnf.cdb
clock1/db/fpga.(10).cnf.hdb
clock1/db/fpga.(11).cnf.cdb
clock1/db/fpga.(11).cnf.hdb
clock1/db/fpga.(12).cnf.cdb
clock1/db/fpga.(12).cnf.hdb
clock1/db/fpga.(13).cnf.cdb
clock1/db/fpga.(13).cnf.hdb
clock1/db/fpga.(14).cnf.cdb
clock1/db/fpga.(14).cnf.hdb
clock1/db/fpga.(15).cnf.cdb
clock1/db/fpga.(15).cnf.hdb
clock1/db/fpga.(16).cnf.cdb
clock1/db/fpga.(16).cnf.hdb
clock1/db/fpga.(17).cnf.cdb
clock1/db/fpga.(17).cnf.hdb
clock1/db/fpga.(18).cnf.cdb
clock1/db/fpga.(18).cnf.hdb
clock1/db/fpga.(2).cnf.cdb
clock1/db/fpga.(2).cnf.hdb
clock1/db/fpga.(3).cnf.cdb
clock1/db/fpga.(3).cnf.hdb
clock1/db/fpga.(4).cnf.cdb
clock1/db/fpga.(4).cnf.hdb
clock1/db/fpga.(5).cnf.cdb
clock1/db/fpga.(5).cnf.hdb
clock1/db/fpga.(6).cnf.cdb
clock1/db/fpga.(6).cnf.hdb
clock1/db/fpga.(7).cnf.cdb
clock1/db/fpga.(7).cnf.hdb
clock1/db/fpga.(8).cnf.cdb
clock1/db/fpga.(8).cnf.hdb
clock1/db/fpga.(9).cnf.cdb
clock1/db/fpga.(9).cnf.hdb
clock1/db/fpga.asm.qmsg
clock1/db/fpga.asm_labs.ddb
clock1/db/fpga.cbx.xml
clock1/db/fpga.cmp.bpm
clock1/db/fpga.cmp.cdb
clock1/db/fpga.cmp.ecobp
clock1/db/fpga.cmp.hdb
clock1/db/fpga.cmp.logdb
clock1/db/fpga.cmp.rdb
clock1/db/fpga.cmp.tdb
clock1/db/fpga.cmp0.ddb
clock1/db/fpga.cmp2.ddb
clock1/db/fpga.cmp_bb.cdb
clock1/db/fpga.cmp_bb.hdb
clock1/db/fpga.cmp_bb.logdb
clock1/db/fpga.cmp_bb.rcf
clock1/db/fpga.dbp
clock1/db/fpga.db_info
clock1/db/fpga.eco.cdb
clock1/db/fpga.fit.qmsg
clock1/db/fpga.hier_info
clock1/db/fpga.hif
clock1/db/fpga.map.bpm
clock1/db/fpga.map.cdb
clock1/db/fpga.map.ecobp
clock1/db/fpga.map.hdb
clock1/db/fpga.map.logdb
clock1/db/fpga.map.qmsg
clock1/db/fpga.map_bb.cdb
clock1/db/fpga.map_bb.hdb
clock1/db/fpga.map_bb.logdb
clock1/db/fpga.pre_map.cdb
clock1/db/fpga.pre_map.hdb
clock1/db/fpga.psp
clock1/db/fpga.pss
clock1/db/fpga.rtlv.hdb
clock1/db/fpga.rtlv_sg.cdb
clock1/db/fpga.rtlv_sg_swap.cdb
clock1/db/fpga.sgdiff.cdb
clock1/db/fpga.sgdiff.hdb
clock1/db/fpga.signalprobe.cdb
clock1/db/fpga.sld_design_entry.sci
clock1/db/fpga.sld_design_entry_dsc.sci
clock1/db/fpga.syn_hier_info
clock1/db/fpga.tan.qmsg
clock1/db/fpga.tis_db_list.ddb
clock1/db/lpm_divide_1em.tdf
clock1/db/lpm_divide_25m.tdf
clock1/db/lpm_divide_46m.tdf
clock1/db/lpm_divide_vcm.tdf
clock1/db/prev_cmp_fpga.asm.qmsg
clock1/db/prev_cmp_fpga.fit.qmsg
clock1/db/prev_cmp_fpga.map.qmsg
clock1/db/prev_cmp_fpga.qmsg
clock1/db/prev_cmp_fpga.tan.qmsg
clock1/db/sign_div_unsign_9kh.tdf
clock1/fenpin.bsf
clock1/fenpin.v
clock1/fenpin.v.bak
clock1/fenpin_1k.bsf
clock1/fenpin_1k.v
clock1/fenpin_1k.v.bak
clock1/fpga.asm.rpt
clock1/fpga.bdf
clock1/fpga.cdf
clock1/fpga.done
clock1/fpga.dpf
clock1/fpga.fit.rpt
clock1/fpga.fit.smsg
clock1/fpga.fit.summary
clock1/fpga.flow.rpt
clock1/fpga.map.rpt
clock1/fpga.map.smsg
clock1/fpga.map.summary
clock1/fpga.pin
clock1/fpga.pof
clock1/fpga.qpf
clock1/fpga.qsf
clock1/fpga.qws
clock1/fpga.sof
clock1/fpga.tan.rpt
clock1/fpga.tan.summary
clock1/fpga.tcl
clock1/fpga.tcl.bak
clock1/kongzhiqi.bsf
clock1/kongzhiqi.v
clock1/kongzhiqi.v.bak
clock1/xianshi.bsf
clock1/xianshi.v
clock1/xianshi.v.bak
clock1/db/
clock1/db/alt_u_div_m0f.tdf
clock1/db/fpga.(0).cnf.cdb
clock1/db/fpga.(0).cnf.hdb
clock1/db/fpga.(1).cnf.cdb
clock1/db/fpga.(1).cnf.hdb
clock1/db/fpga.(10).cnf.cdb
clock1/db/fpga.(10).cnf.hdb
clock1/db/fpga.(11).cnf.cdb
clock1/db/fpga.(11).cnf.hdb
clock1/db/fpga.(12).cnf.cdb
clock1/db/fpga.(12).cnf.hdb
clock1/db/fpga.(13).cnf.cdb
clock1/db/fpga.(13).cnf.hdb
clock1/db/fpga.(14).cnf.cdb
clock1/db/fpga.(14).cnf.hdb
clock1/db/fpga.(15).cnf.cdb
clock1/db/fpga.(15).cnf.hdb
clock1/db/fpga.(16).cnf.cdb
clock1/db/fpga.(16).cnf.hdb
clock1/db/fpga.(17).cnf.cdb
clock1/db/fpga.(17).cnf.hdb
clock1/db/fpga.(18).cnf.cdb
clock1/db/fpga.(18).cnf.hdb
clock1/db/fpga.(2).cnf.cdb
clock1/db/fpga.(2).cnf.hdb
clock1/db/fpga.(3).cnf.cdb
clock1/db/fpga.(3).cnf.hdb
clock1/db/fpga.(4).cnf.cdb
clock1/db/fpga.(4).cnf.hdb
clock1/db/fpga.(5).cnf.cdb
clock1/db/fpga.(5).cnf.hdb
clock1/db/fpga.(6).cnf.cdb
clock1/db/fpga.(6).cnf.hdb
clock1/db/fpga.(7).cnf.cdb
clock1/db/fpga.(7).cnf.hdb
clock1/db/fpga.(8).cnf.cdb
clock1/db/fpga.(8).cnf.hdb
clock1/db/fpga.(9).cnf.cdb
clock1/db/fpga.(9).cnf.hdb
clock1/db/fpga.asm.qmsg
clock1/db/fpga.asm_labs.ddb
clock1/db/fpga.cbx.xml
clock1/db/fpga.cmp.bpm
clock1/db/fpga.cmp.cdb
clock1/db/fpga.cmp.ecobp
clock1/db/fpga.cmp.hdb
clock1/db/fpga.cmp.logdb
clock1/db/fpga.cmp.rdb
clock1/db/fpga.cmp.tdb
clock1/db/fpga.cmp0.ddb
clock1/db/fpga.cmp2.ddb
clock1/db/fpga.cmp_bb.cdb
clock1/db/fpga.cmp_bb.hdb
clock1/db/fpga.cmp_bb.logdb
clock1/db/fpga.cmp_bb.rcf
clock1/db/fpga.dbp
clock1/db/fpga.db_info
clock1/db/fpga.eco.cdb
clock1/db/fpga.fit.qmsg
clock1/db/fpga.hier_info
clock1/db/fpga.hif
clock1/db/fpga.map.bpm
clock1/db/fpga.map.cdb
clock1/db/fpga.map.ecobp
clock1/db/fpga.map.hdb
clock1/db/fpga.map.logdb
clock1/db/fpga.map.qmsg
clock1/db/fpga.map_bb.cdb
clock1/db/fpga.map_bb.hdb
clock1/db/fpga.map_bb.logdb
clock1/db/fpga.pre_map.cdb
clock1/db/fpga.pre_map.hdb
clock1/db/fpga.psp
clock1/db/fpga.pss
clock1/db/fpga.rtlv.hdb
clock1/db/fpga.rtlv_sg.cdb
clock1/db/fpga.rtlv_sg_swap.cdb
clock1/db/fpga.sgdiff.cdb
clock1/db/fpga.sgdiff.hdb
clock1/db/fpga.signalprobe.cdb
clock1/db/fpga.sld_design_entry.sci
clock1/db/fpga.sld_design_entry_dsc.sci
clock1/db/fpga.syn_hier_info
clock1/db/fpga.tan.qmsg
clock1/db/fpga.tis_db_list.ddb
clock1/db/lpm_divide_1em.tdf
clock1/db/lpm_divide_25m.tdf
clock1/db/lpm_divide_46m.tdf
clock1/db/lpm_divide_vcm.tdf
clock1/db/prev_cmp_fpga.asm.qmsg
clock1/db/prev_cmp_fpga.fit.qmsg
clock1/db/prev_cmp_fpga.map.qmsg
clock1/db/prev_cmp_fpga.qmsg
clock1/db/prev_cmp_fpga.tan.qmsg
clock1/db/sign_div_unsign_9kh.tdf
clock1/fenpin.bsf
clock1/fenpin.v
clock1/fenpin.v.bak
clock1/fenpin_1k.bsf
clock1/fenpin_1k.v
clock1/fenpin_1k.v.bak
clock1/fpga.asm.rpt
clock1/fpga.bdf
clock1/fpga.cdf
clock1/fpga.done
clock1/fpga.dpf
clock1/fpga.fit.rpt
clock1/fpga.fit.smsg
clock1/fpga.fit.summary
clock1/fpga.flow.rpt
clock1/fpga.map.rpt
clock1/fpga.map.smsg
clock1/fpga.map.summary
clock1/fpga.pin
clock1/fpga.pof
clock1/fpga.qpf
clock1/fpga.qsf
clock1/fpga.qws
clock1/fpga.sof
clock1/fpga.tan.rpt
clock1/fpga.tan.summary
clock1/fpga.tcl
clock1/fpga.tcl.bak
clock1/kongzhiqi.bsf
clock1/kongzhiqi.v
clock1/kongzhiqi.v.bak
clock1/xianshi.bsf
clock1/xianshi.v
clock1/xianshi.v.bak
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