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文件名称:fpga-fir

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [C/C++] [源码]
  • 上传时间：
    2013-03-16
  • 文件大小：
    982.65kb
  • 已下载：
    0次
  • 提 供 者：
    bam***
  • 相关连接：
    无
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

xlinx fpga 利用verilog语言实现fir滤波器功能，完整ise工程文件直接可以使用-xlinx fpga verilog language the fir filter function, complete ise project file can be used directly
(系统自动生成,下载前可以参看下载内容)

下载文件列表

fpga fir/coregen_xil_2600_47.cgc
fpga fir/coregen_xil_2600_47.cgp
fpga fir/fir_core.mif
fpga fir/fir_coreCOEFF_auto0_0.mif
fpga fir/fir_coreCOEFF_auto0_1.mif
fpga fir/fir_coreCOEFF_auto0_2.mif
fpga fir/fir_coreCOEFF_auto0_3.mif
fpga fir/fir_coreCOEFF_auto0_4.mif
fpga fir/fir_coreCOEFF_auto0_5.mif
fpga fir/fir_coreCOEFF_auto0_6.mif
fpga fir/fir_coreCOEFF_auto0_7.mif
fpga fir/fir_coreCOEFF_auto0_8.mif
fpga fir/fir_coreCOEFF_auto0_9.mif
fpga fir/fir_corefilt_decode_rom.mif
fpga fir/fir_data.coe
fpga fir/fir_demo.gise
fpga fir/fir_demo.xise
fpga fir/fir_top.v
fpga fir/fir_top_summary.html
fpga fir/fuse.log
fpga fir/fuse.xmsgs
fpga fir/fuseRelaunch.cmd
fpga fir/ipcore_dir/.lso
fpga fir/ipcore_dir/coregen.log
fpga fir/ipcore_dir/edit_fir_core.tcl
fpga fir/ipcore_dir/fir_compiler_v5_0.asy
fpga fir/ipcore_dir/fir_compiler_v5_0.gise
fpga fir/ipcore_dir/fir_compiler_v5_0.mif
fpga fir/ipcore_dir/fir_compiler_v5_0.ngc
fpga fir/ipcore_dir/fir_compiler_v5_0.sym
fpga fir/ipcore_dir/fir_compiler_v5_0.v
fpga fir/ipcore_dir/fir_compiler_v5_0.veo
fpga fir/ipcore_dir/fir_compiler_v5_0.xco
fpga fir/ipcore_dir/fir_compiler_v5_0.xise
fpga fir/ipcore_dir/fir_compiler_v5_0COEFF_auto0_0.mif
fpga fir/ipcore_dir/fir_compiler_v5_0COEFF_auto0_1.mif
fpga fir/ipcore_dir/fir_compiler_v5_0COEFF_auto0_2.mif
fpga fir/ipcore_dir/fir_compiler_v5_0COEFF_auto0_3.mif
fpga fir/ipcore_dir/fir_compiler_v5_0COEFF_auto0_4.mif
fpga fir/ipcore_dir/fir_compiler_v5_0filt_decode_rom.mif
fpga fir/ipcore_dir/fir_compiler_v5_0_flist.txt
fpga fir/ipcore_dir/fir_compiler_v5_0_readme.txt
fpga fir/ipcore_dir/fir_compiler_v5_0_xmdf.tcl
fpga fir/ipcore_dir/fir_core.asy
fpga fir/ipcore_dir/fir_core.gise
fpga fir/ipcore_dir/fir_core.mif
fpga fir/ipcore_dir/fir_core.ngc
fpga fir/ipcore_dir/fir_core.sym
fpga fir/ipcore_dir/fir_core.v
fpga fir/ipcore_dir/fir_core.veo
fpga fir/ipcore_dir/fir_core.vhd
fpga fir/ipcore_dir/fir_core.vho
fpga fir/ipcore_dir/fir_core.xco
fpga fir/ipcore_dir/fir_core.xise
fpga fir/ipcore_dir/fir_coreCOEFF_auto0_0.mif
fpga fir/ipcore_dir/fir_coreCOEFF_auto0_1.mif
fpga fir/ipcore_dir/fir_coreCOEFF_auto0_2.mif
fpga fir/ipcore_dir/fir_coreCOEFF_auto0_3.mif
fpga fir/ipcore_dir/fir_coreCOEFF_auto0_4.mif
fpga fir/ipcore_dir/fir_coreCOEFF_auto0_5.mif
fpga fir/ipcore_dir/fir_coreCOEFF_auto0_6.mif
fpga fir/ipcore_dir/fir_coreCOEFF_auto0_7.mif
fpga fir/ipcore_dir/fir_coreCOEFF_auto0_8.mif
fpga fir/ipcore_dir/fir_coreCOEFF_auto0_9.mif
fpga fir/ipcore_dir/fir_corefilt_decode_rom.mif
fpga fir/ipcore_dir/fir_core_flist.txt
fpga fir/ipcore_dir/fir_core_readme.txt
fpga fir/ipcore_dir/fir_core_xmdf.tcl
fpga fir/ipcore_dir/tmp/_xmsgs/netgen.xmsgs
fpga fir/ipcore_dir/tmp/_xmsgs/ngcbuild.xmsgs
fpga fir/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs
fpga fir/ipcore_dir/tmp/_xmsgs/xst.xmsgs
fpga fir/ipcore_dir/_xmsgs/cg.xmsgs
fpga fir/ipcore_dir/_xmsgs/pn_parser.xmsgs
fpga fir/iseconfig/fir_demo.projectmgr
fpga fir/iseconfig/fir_top.xreport
fpga fir/isim/isim_usage_statistics.html
fpga fir/isim/pn_info
fpga fir/isim/tb_fir_top_isim_beh.exe.sim/isimcrash.log
fpga fir/isim/tb_fir_top_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
fpga fir/isim/tb_fir_top_isim_beh.exe.sim/isimkernel.log
fpga fir/isim/tb_fir_top_isim_beh.exe.sim/libPortability.dll
fpga fir/isim/tb_fir_top_isim_beh.exe.sim/netId.dat
fpga fir/isim/tb_fir_top_isim_beh.exe.sim/tb_fir_top_isim_beh.exe
fpga fir/isim/tb_fir_top_isim_beh.exe.sim/tmp_save/_1
fpga fir/isim/tb_fir_top_isim_beh.exe.sim/unisims_ver/m_00000000000073490608_3589000630.c
fpga fir/isim/tb_fir_top_isim_beh.exe.sim/unisims_ver/m_00000000000073490608_3589000630.didat
fpga fir/isim/tb_fir_top_isim_beh.exe.sim/unisims_ver/m_00000000000073490608_3589000630.nt64.obj
fpga fir/isim/tb_fir_top_isim_beh.exe.sim/unisims_ver/m_00000000000129024098_1730278898.c
fpga fir/isim/tb_fir_top_isim_beh.exe.sim/unisims_ver/m_00000000000129024098_1730278898.didat
fpga fir/isim/tb_fir_top_isim_beh.exe.sim/unisims_ver/m_00000000000129024098_1730278898.nt64.obj
fpga fir/isim/tb_fir_top_isim_beh.exe.sim/unisims_ver/m_00000000000236260522_2449448540.c
fpga fir/isim/tb_fir_top_isim_beh.exe.sim/unisims_ver/m_00000000000236260522_2449448540.didat
fpga fir/isim/tb_fir_top_isim_beh.exe.sim/unisims_ver/m_00000000000236260522_2449448540.nt64.obj
fpga fir/isim/tb_fir_top_isim_beh.exe.sim/unisims_ver/m_00000000000909115699_2771340377.c
fpga fir/isim/tb_fir_top_isim_beh.exe.sim/unisims_ver/m_00000000000909115699_2771340377.didat
fpga fir/isim/tb_fir_top_isim_beh.exe.sim/unisims_ver/m_00000000000909115699_2771340377.nt64.obj
fpga fir/isim/tb_fir_top_isim_beh.exe.sim/unisims_ver/m_00000000001108370118_0289162403.c
fpga fir/isim/tb_fir_top_isim_beh.exe.sim/unisims_ver/m_00000000001108370118_0289162403.didat
fpga fir/isim/tb_fir_top_isim_beh.exe.sim/unisims_ver/m_00000000001108370118_0289162403.nt64.obj
fpga fir/isim/tb_fir_top_isim_beh.exe.sim/unisims_ver/m_00000000001508379050_3852734344.c
fpga fir/isim/tb_fir_top_isim_beh.exe.sim/unisims_ver/m_00000000001508379050_3852734344.didat
fpga fir/isim/tb_fir_top_isim_beh.exe.sim/unisims_ver/m_00000000001508379050_3852734344.nt64.obj
fpga fir/isim/tb_fir_top_isi

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