文件名称:oc8051
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- 上传时间:2008-10-13
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文件大小:1.17mb
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已下载:1次
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8051的verilog实现,内附testbench,c语言调试程序-8051 verilog achieve, enclosing testbench, c language debugging procedures
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下载文件列表
oc8051/.nclaunch.dd
oc8051/syn/synplify/oc8051.prd
oc8051/syn/synplify/oc8051.prj
oc8051/syn/synplify/rev_3/CVS/Entries
oc8051/syn/synplify/rev_3/CVS/Repository
oc8051/syn/synplify/rev_3/CVS/Root
oc8051/syn/synplify/rev_3/CVS
oc8051/syn/synplify/rev_3
oc8051/syn/synplify/rev_2/CVS/Entries
oc8051/syn/synplify/rev_2/CVS/Repository
oc8051/syn/synplify/rev_2/CVS/Root
oc8051/syn/synplify/rev_2/CVS
oc8051/syn/synplify/rev_2
oc8051/syn/synplify/rev_1/CVS/Entries
oc8051/syn/synplify/rev_1/CVS/Repository
oc8051/syn/synplify/rev_1/CVS/Root
oc8051/syn/synplify/rev_1/CVS
oc8051/syn/synplify/rev_1
oc8051/syn/synplify/CVS/Entries
oc8051/syn/synplify/CVS/Repository
oc8051/syn/synplify/CVS/Root
oc8051/syn/synplify/CVS
oc8051/syn/synplify
oc8051/syn/src/verilog/disp.v
oc8051/syn/src/verilog/oc8051_cache_ram.v
oc8051/syn/src/verilog/oc8051_fpga_top.v
oc8051/syn/src/verilog/oc8051_ram.v
oc8051/syn/src/verilog/oc8051_rom.v
oc8051/syn/src/verilog/read.me
oc8051/syn/src/verilog/CVS/Entries
oc8051/syn/src/verilog/CVS/Repository
oc8051/syn/src/verilog/CVS/Root
oc8051/syn/src/verilog/CVS
oc8051/syn/src/verilog
oc8051/syn/src/CVS/Entries
oc8051/syn/src/CVS/Repository
oc8051/syn/src/CVS/Root
oc8051/syn/src/CVS
oc8051/syn/src
oc8051/syn/CVS/Entries
oc8051/syn/CVS/Repository
oc8051/syn/CVS/Root
oc8051/syn/CVS
oc8051/syn
oc8051/sw/oc8051_Rom_Maker.exe
oc8051/sw/read.me
oc8051/sw/source/p8051Rom.dof
oc8051/sw/source/p8051Rom.dpr
oc8051/sw/source/p8051Rom.res
oc8051/sw/source/uMain.dcu
oc8051/sw/source/uMain.dfm
oc8051/sw/source/uMain.pas
oc8051/sw/source/CVS/Entries
oc8051/sw/source/CVS/Repository
oc8051/sw/source/CVS/Root
oc8051/sw/source/CVS
oc8051/sw/source
oc8051/sw/CVS/Entries
oc8051/sw/CVS/Repository
oc8051/sw/CVS/Root
oc8051/sw/CVS
oc8051/sw
oc8051/sim/rtl_sim/oc8051_ea.in
oc8051/sim/rtl_sim/oc8051_eai.in
oc8051/sim/rtl_sim/oc8051_eax.in
oc8051/sim/rtl_sim/src/verilog/CVS/Entries
oc8051/sim/rtl_sim/src/verilog/CVS/Repository
oc8051/sim/rtl_sim/src/verilog/CVS/Root
oc8051/sim/rtl_sim/src/verilog/CVS
oc8051/sim/rtl_sim/src/verilog
oc8051/sim/rtl_sim/src/CVS/Entries
oc8051/sim/rtl_sim/src/CVS/Repository
oc8051/sim/rtl_sim/src/CVS/Root
oc8051/sim/rtl_sim/src/CVS
oc8051/sim/rtl_sim/src
oc8051/sim/rtl_sim/run/internal.do
oc8051/sim/rtl_sim/run/make
oc8051/sim/rtl_sim/run/make_fpga
oc8051/sim/rtl_sim/run/make_verilog
oc8051/sim/rtl_sim/run/oc8051_defines.v
oc8051/sim/rtl_sim/run/oc8051_timescale.v
oc8051/sim/rtl_sim/run/run
oc8051/sim/rtl_sim/run/run_sim.scr
oc8051/sim/rtl_sim/run/verilog.log
oc8051/sim/rtl_sim/run/CVS/Entries
oc8051/sim/rtl_sim/run/CVS/Repository
oc8051/sim/rtl_sim/run/CVS/Root
oc8051/sim/rtl_sim/run/CVS
oc8051/sim/rtl_sim/run
oc8051/sim/rtl_sim/out/cast.out
oc8051/sim/rtl_sim/out/counter_test.out
oc8051/sim/rtl_sim/out/div16u.out
oc8051/sim/rtl_sim/out/divmul.out
oc8051/sim/rtl_sim/out/fib.out
oc8051/sim/rtl_sim/out/gcd.out
oc8051/sim/rtl_sim/out/int2bin.out
oc8051/sim/rtl_sim/out/interrupt_test.out
oc8051/sim/rtl_sim/out/lcall.out
oc8051/sim/rtl_sim/out/ncelab.out
oc8051/sim/rtl_sim/out/ncprep.out
oc8051/sim/rtl_sim/out/ncvlog.out
oc8051/sim/rtl_sim/out/negcnt.out
oc8051/sim/rtl_sim/out/r_bank.out
oc8051/sim/rtl_sim/out/serial_test.out
oc8051/sim/rtl_sim/out/sort.out
oc8051/sim/rtl_sim/out/sqroot.out
oc8051/sim/rtl_sim/out/testall.out
oc8051/sim/rtl_sim/out/timer.out
oc8051/sim/rtl_sim/out/timer_test.out
oc8051/sim/rtl_sim/out/xram_m.out
oc8051/sim/rtl_sim/out/xrom_m.out
oc8051/sim/rtl_sim/out/waves.shm/CVS/Entries
oc8051/sim/rtl_sim/out/waves.shm/CVS/Repository
oc8051/sim/rtl_sim/out/waves.shm/CVS/Root
oc8051/sim/rtl_sim/out/waves.shm/CVS
oc8051/sim/rtl_sim/out/waves.shm
oc8051/sim/rtl_sim/out/CVS/Entries
oc8051/sim/rtl_sim/out/CVS/Repository
oc8051/sim/rtl_sim/out/CVS/Root
oc8051/sim/rtl_sim/out/CVS
oc8051/sim/rtl_sim/out
oc8051/sim/rtl_sim/log/ncelab.log
oc8051/sim/rtl_sim/log/ncsim.log
oc8051/sim/rtl_sim/log/ncvlog.log
oc8051/sim/rtl_sim/log/CVS/Entries
oc8051/sim/rtl_sim/log/CVS/Repository
oc8051/sim/rtl_sim/log/CVS/Root
oc8051/sim/rtl_sim/log/CVS
oc8051/sim/rtl_sim/log
oc8051/sim/rtl_sim/CVS/Entries
oc8051/sim/rtl_sim/CVS/Repository
oc8051/sim/rtl_sim/CVS/Root
oc8051/sim/rtl_sim/CVS
oc8051/sim/rtl_sim/bin/cds.lib
oc8051/sim/rtl_sim/bin/hdl.var
oc8051/sim/rtl_sim/bin/INCA_libs/worklib/inca.linux.138.pak
oc8051/sim/rtl_sim/bin/INCA_libs/worklib/CVS/Entries
oc8051/sim/rtl_sim/bin/INCA_libs/worklib/CVS/Repository
oc8051/sim/rtl_sim/bin/INCA_libs/worklib/CVS/Root
oc8051/sim/rtl_sim/bin/INCA_libs/worklib/CVS
oc8051/sim/rtl_sim/bin/INCA_libs/worklib
oc8051/sim/rtl_sim/bin/INCA_libs/CVS/Entries
oc8051/sim/rtl_sim/bin/INCA_libs/CVS/Repository
oc8051/sim/rtl_sim/bin/INCA_libs/CVS/Root
oc8051/sim/rtl_sim/bin/INCA_libs/CVS
oc8051/sim/rtl_sim/bin/INCA_libs
oc8051/sim/rtl_sim/bin/CVS/Entries
oc8051/sim/rtl_sim/bin/CVS/Repository
oc8051/sim/rtl_sim/bin/CVS/Root
oc8051/sim/rtl_sim/bin/CVS
oc8051/sim/rtl_sim/bin
oc8051/sim/rtl_sim
oc8051/sim/CVS/Entries
oc8051/sim/CVS/Repository
oc8051/sim/CVS/Root
oc8051/sim/CVS
oc8051/sim
oc8051/rtl/verilog/oc8051_acc.v
oc8051/rtl/verilog/oc8051_alu.v
oc8051/rtl/verilog/oc8051_alu_src_sel.v
oc8051/rtl/verilog/o
oc8051/syn/synplify/oc8051.prd
oc8051/syn/synplify/oc8051.prj
oc8051/syn/synplify/rev_3/CVS/Entries
oc8051/syn/synplify/rev_3/CVS/Repository
oc8051/syn/synplify/rev_3/CVS/Root
oc8051/syn/synplify/rev_3/CVS
oc8051/syn/synplify/rev_3
oc8051/syn/synplify/rev_2/CVS/Entries
oc8051/syn/synplify/rev_2/CVS/Repository
oc8051/syn/synplify/rev_2/CVS/Root
oc8051/syn/synplify/rev_2/CVS
oc8051/syn/synplify/rev_2
oc8051/syn/synplify/rev_1/CVS/Entries
oc8051/syn/synplify/rev_1/CVS/Repository
oc8051/syn/synplify/rev_1/CVS/Root
oc8051/syn/synplify/rev_1/CVS
oc8051/syn/synplify/rev_1
oc8051/syn/synplify/CVS/Entries
oc8051/syn/synplify/CVS/Repository
oc8051/syn/synplify/CVS/Root
oc8051/syn/synplify/CVS
oc8051/syn/synplify
oc8051/syn/src/verilog/disp.v
oc8051/syn/src/verilog/oc8051_cache_ram.v
oc8051/syn/src/verilog/oc8051_fpga_top.v
oc8051/syn/src/verilog/oc8051_ram.v
oc8051/syn/src/verilog/oc8051_rom.v
oc8051/syn/src/verilog/read.me
oc8051/syn/src/verilog/CVS/Entries
oc8051/syn/src/verilog/CVS/Repository
oc8051/syn/src/verilog/CVS/Root
oc8051/syn/src/verilog/CVS
oc8051/syn/src/verilog
oc8051/syn/src/CVS/Entries
oc8051/syn/src/CVS/Repository
oc8051/syn/src/CVS/Root
oc8051/syn/src/CVS
oc8051/syn/src
oc8051/syn/CVS/Entries
oc8051/syn/CVS/Repository
oc8051/syn/CVS/Root
oc8051/syn/CVS
oc8051/syn
oc8051/sw/oc8051_Rom_Maker.exe
oc8051/sw/read.me
oc8051/sw/source/p8051Rom.dof
oc8051/sw/source/p8051Rom.dpr
oc8051/sw/source/p8051Rom.res
oc8051/sw/source/uMain.dcu
oc8051/sw/source/uMain.dfm
oc8051/sw/source/uMain.pas
oc8051/sw/source/CVS/Entries
oc8051/sw/source/CVS/Repository
oc8051/sw/source/CVS/Root
oc8051/sw/source/CVS
oc8051/sw/source
oc8051/sw/CVS/Entries
oc8051/sw/CVS/Repository
oc8051/sw/CVS/Root
oc8051/sw/CVS
oc8051/sw
oc8051/sim/rtl_sim/oc8051_ea.in
oc8051/sim/rtl_sim/oc8051_eai.in
oc8051/sim/rtl_sim/oc8051_eax.in
oc8051/sim/rtl_sim/src/verilog/CVS/Entries
oc8051/sim/rtl_sim/src/verilog/CVS/Repository
oc8051/sim/rtl_sim/src/verilog/CVS/Root
oc8051/sim/rtl_sim/src/verilog/CVS
oc8051/sim/rtl_sim/src/verilog
oc8051/sim/rtl_sim/src/CVS/Entries
oc8051/sim/rtl_sim/src/CVS/Repository
oc8051/sim/rtl_sim/src/CVS/Root
oc8051/sim/rtl_sim/src/CVS
oc8051/sim/rtl_sim/src
oc8051/sim/rtl_sim/run/internal.do
oc8051/sim/rtl_sim/run/make
oc8051/sim/rtl_sim/run/make_fpga
oc8051/sim/rtl_sim/run/make_verilog
oc8051/sim/rtl_sim/run/oc8051_defines.v
oc8051/sim/rtl_sim/run/oc8051_timescale.v
oc8051/sim/rtl_sim/run/run
oc8051/sim/rtl_sim/run/run_sim.scr
oc8051/sim/rtl_sim/run/verilog.log
oc8051/sim/rtl_sim/run/CVS/Entries
oc8051/sim/rtl_sim/run/CVS/Repository
oc8051/sim/rtl_sim/run/CVS/Root
oc8051/sim/rtl_sim/run/CVS
oc8051/sim/rtl_sim/run
oc8051/sim/rtl_sim/out/cast.out
oc8051/sim/rtl_sim/out/counter_test.out
oc8051/sim/rtl_sim/out/div16u.out
oc8051/sim/rtl_sim/out/divmul.out
oc8051/sim/rtl_sim/out/fib.out
oc8051/sim/rtl_sim/out/gcd.out
oc8051/sim/rtl_sim/out/int2bin.out
oc8051/sim/rtl_sim/out/interrupt_test.out
oc8051/sim/rtl_sim/out/lcall.out
oc8051/sim/rtl_sim/out/ncelab.out
oc8051/sim/rtl_sim/out/ncprep.out
oc8051/sim/rtl_sim/out/ncvlog.out
oc8051/sim/rtl_sim/out/negcnt.out
oc8051/sim/rtl_sim/out/r_bank.out
oc8051/sim/rtl_sim/out/serial_test.out
oc8051/sim/rtl_sim/out/sort.out
oc8051/sim/rtl_sim/out/sqroot.out
oc8051/sim/rtl_sim/out/testall.out
oc8051/sim/rtl_sim/out/timer.out
oc8051/sim/rtl_sim/out/timer_test.out
oc8051/sim/rtl_sim/out/xram_m.out
oc8051/sim/rtl_sim/out/xrom_m.out
oc8051/sim/rtl_sim/out/waves.shm/CVS/Entries
oc8051/sim/rtl_sim/out/waves.shm/CVS/Repository
oc8051/sim/rtl_sim/out/waves.shm/CVS/Root
oc8051/sim/rtl_sim/out/waves.shm/CVS
oc8051/sim/rtl_sim/out/waves.shm
oc8051/sim/rtl_sim/out/CVS/Entries
oc8051/sim/rtl_sim/out/CVS/Repository
oc8051/sim/rtl_sim/out/CVS/Root
oc8051/sim/rtl_sim/out/CVS
oc8051/sim/rtl_sim/out
oc8051/sim/rtl_sim/log/ncelab.log
oc8051/sim/rtl_sim/log/ncsim.log
oc8051/sim/rtl_sim/log/ncvlog.log
oc8051/sim/rtl_sim/log/CVS/Entries
oc8051/sim/rtl_sim/log/CVS/Repository
oc8051/sim/rtl_sim/log/CVS/Root
oc8051/sim/rtl_sim/log/CVS
oc8051/sim/rtl_sim/log
oc8051/sim/rtl_sim/CVS/Entries
oc8051/sim/rtl_sim/CVS/Repository
oc8051/sim/rtl_sim/CVS/Root
oc8051/sim/rtl_sim/CVS
oc8051/sim/rtl_sim/bin/cds.lib
oc8051/sim/rtl_sim/bin/hdl.var
oc8051/sim/rtl_sim/bin/INCA_libs/worklib/inca.linux.138.pak
oc8051/sim/rtl_sim/bin/INCA_libs/worklib/CVS/Entries
oc8051/sim/rtl_sim/bin/INCA_libs/worklib/CVS/Repository
oc8051/sim/rtl_sim/bin/INCA_libs/worklib/CVS/Root
oc8051/sim/rtl_sim/bin/INCA_libs/worklib/CVS
oc8051/sim/rtl_sim/bin/INCA_libs/worklib
oc8051/sim/rtl_sim/bin/INCA_libs/CVS/Entries
oc8051/sim/rtl_sim/bin/INCA_libs/CVS/Repository
oc8051/sim/rtl_sim/bin/INCA_libs/CVS/Root
oc8051/sim/rtl_sim/bin/INCA_libs/CVS
oc8051/sim/rtl_sim/bin/INCA_libs
oc8051/sim/rtl_sim/bin/CVS/Entries
oc8051/sim/rtl_sim/bin/CVS/Repository
oc8051/sim/rtl_sim/bin/CVS/Root
oc8051/sim/rtl_sim/bin/CVS
oc8051/sim/rtl_sim/bin
oc8051/sim/rtl_sim
oc8051/sim/CVS/Entries
oc8051/sim/CVS/Repository
oc8051/sim/CVS/Root
oc8051/sim/CVS
oc8051/sim
oc8051/rtl/verilog/oc8051_acc.v
oc8051/rtl/verilog/oc8051_alu.v
oc8051/rtl/verilog/oc8051_alu_src_sel.v
oc8051/rtl/verilog/o
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