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文件名称:05_UART_demo

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [C/C++] [源码]
  • 上传时间：
    2013-04-13
  • 文件大小：
    886.55kb
  • 已下载：
    0次
  • 提 供 者：
    duji****
  • 相关连接：
    无
  • 下载说明：
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

该UART实例是很简单的EDK工程，在PLB总线上挂载了XPS-uartlite外围设备，作为串口的控制器，一般的EDK工程会将该IP作为基本外围设备来使用。包含bit流文件(在EDK上下载到FPGA上使用），和说明文档。-The UART instance EDK project is very simple and is mounted on the PLB bus the XPS-uartlite peripherals, general EDK works as a serial controller, the IP to use as a basic peripherals. Contains bit stream file downloaded to the FPGA (EDK on use), and documentation.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

05_UART_demo/
05_UART_demo/Genesys_UART_demo_EDK/
05_UART_demo/Genesys_UART_demo_EDK/bitinit.log
05_UART_demo/Genesys_UART_demo_EDK/blockdiagram/
05_UART_demo/Genesys_UART_demo_EDK/clock_generator_0.log
05_UART_demo/Genesys_UART_demo_EDK/data/
05_UART_demo/Genesys_UART_demo_EDK/data/system.ucf
05_UART_demo/Genesys_UART_demo_EDK/etc/
05_UART_demo/Genesys_UART_demo_EDK/etc/bitgen.ut
05_UART_demo/Genesys_UART_demo_EDK/etc/download.cmd
05_UART_demo/Genesys_UART_demo_EDK/etc/fast_runtime.opt
05_UART_demo/Genesys_UART_demo_EDK/pcores/
05_UART_demo/Genesys_UART_demo_EDK/platgen.opt
05_UART_demo/Genesys_UART_demo_EDK/psf2Edward.log
05_UART_demo/Genesys_UART_demo_EDK/system.bsb
05_UART_demo/Genesys_UART_demo_EDK/system.log
05_UART_demo/Genesys_UART_demo_EDK/system.make
05_UART_demo/Genesys_UART_demo_EDK/system.mhs
05_UART_demo/Genesys_UART_demo_EDK/system.mss
05_UART_demo/Genesys_UART_demo_EDK/system.xmp
05_UART_demo/Genesys_UART_demo_EDK/system_incl.make
05_UART_demo/Genesys_UART_demo_EDK/TestApp_UART_Demo_microblaze_0/
05_UART_demo/Genesys_UART_demo_EDK/TestApp_UART_Demo_microblaze_0/UART_Demo.c
05_UART_demo/Genesys_UART_demo_EDK/UART_Demo/
05_UART_demo/Genesys_UART_demo_EDK/XpsGuiSessionLock
05_UART_demo/Genesys_UART_demo_EDK/_impactbatch.log
05_UART_demo/Genesys_UART_demo_EDK/__xps/
05_UART_demo/Genesys_UART_demo_EDK/__xps/.dswkshop/
05_UART_demo/Genesys_UART_demo_EDK/__xps/.dswkshop/MdtSvgBLKD_Dimensions.xsl
05_UART_demo/Genesys_UART_demo_EDK/__xps/.dswkshop/MdtSvgDiag_Colors.xsl
05_UART_demo/Genesys_UART_demo_EDK/__xps/.dswkshop/MdtSvgDiag_Globals.xsl
05_UART_demo/Genesys_UART_demo_EDK/__xps/.dswkshop/MdtSvgDiag_StyleDefs.xsl
05_UART_demo/Genesys_UART_demo_EDK/__xps/.dswkshop/MdtTinySvgBLKD_BusLaneSpaces.xsl
05_UART_demo/Genesys_UART_demo_EDK/__xps/.dswkshop/MdtTinySvgBLKD_Busses.xsl
05_UART_demo/Genesys_UART_demo_EDK/__xps/.dswkshop/MdtTinySvgBLKD_Functions.xsl
05_UART_demo/Genesys_UART_demo_EDK/__xps/.dswkshop/MdtTinySvgBLKD_Globals.xsl
05_UART_demo/Genesys_UART_demo_EDK/__xps/.dswkshop/MdtTinySvgBLKD_IOPorts.xsl
05_UART_demo/Genesys_UART_demo_EDK/__xps/.dswkshop/MdtTinySvgBLKD_Main.xsl
05_UART_demo/Genesys_UART_demo_EDK/__xps/.dswkshop/MdtTinySvgBLKD_Peripherals.xsl
05_UART_demo/Genesys_UART_demo_EDK/__xps/.dswkshop/MdtTinySvgBLKD_Processors.xsl
05_UART_demo/Genesys_UART_demo_EDK/__xps/.dswkshop/MdtTinySvgDiag_BifShapes.xsl
05_UART_demo/Genesys_UART_demo_EDK/__xps/.dswkshop/svg10.dtd
05_UART_demo/Genesys_UART_demo_EDK/__xps/bitinit.opt
05_UART_demo/Genesys_UART_demo_EDK/__xps/ise/
05_UART_demo/Genesys_UART_demo_EDK/__xps/ise/system.gise
05_UART_demo/Genesys_UART_demo_EDK/__xps/ise/system.ise
05_UART_demo/Genesys_UART_demo_EDK/__xps/ise/system.xise
05_UART_demo/Genesys_UART_demo_EDK/__xps/ise/system_xdb/
05_UART_demo/Genesys_UART_demo_EDK/__xps/ise/system_xdb/cst.xbcd
05_UART_demo/Genesys_UART_demo_EDK/__xps/ise/system_xdb/tmp/
05_UART_demo/Genesys_UART_demo_EDK/__xps/ise/system_xdb/tmp/ise/
05_UART_demo/Genesys_UART_demo_EDK/__xps/ise/system_xdb/tmp/ise.lock
05_UART_demo/Genesys_UART_demo_EDK/__xps/ise/system_xdb/tmp/ise/version
05_UART_demo/Genesys_UART_demo_EDK/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/
05_UART_demo/Genesys_UART_demo_EDK/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/Autonym/
05_UART_demo/Genesys_UART_demo_EDK/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/common/
05_UART_demo/Genesys_UART_demo_EDK/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/
05_UART_demo/Genesys_UART_demo_EDK/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/
05_UART_demo/Genesys_UART_demo_EDK/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject
05_UART_demo/Genesys_UART_demo_EDK/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject_StrTbl
05_UART_demo/Genesys_UART_demo_EDK/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/
05_UART_demo/Genesys_UART_demo_EDK/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts/
05_UART_demo/Genesys_UART_demo_EDK/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl
05_UART_demo/Genesys_UART_demo_EDK/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl_StrTbl
05_UART_demo/Genesys_UART_demo_EDK/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/
05_UART_demo/Genesys_UART_demo_EDK/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator11/
05_UART_demo/Genesys_UART_demo_EDK/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/
05_UART_demo/Genesys_UART_demo_EDK/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main
05_UART_demo/Genesys_UART_demo_EDK/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main_StrTbl
05_UART_demo/Genesys_UART_demo_EDK/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/xreport/
05_UART_demo/Genesys_UART_demo_EDK/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Current-Module
05_UART_demo/Genesys_UART_demo_EDK/__xps/ise/system_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Current-Module_StrTbl
05_UART_demo/Genesys_UART_demo_EDK/__xps/i

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