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文件名称:uartfifo

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    2013-04-25
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    884.93kb
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介绍说明--下载内容来自于网络,使用问题请自行百度

以Proasic3 Start kit开发板为平台,介绍了FIFO的基本功能。-ProASIC3 Start Kit development board as a platform to introduce the basic functions of the FIFO.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

uartfifo/designer/impl1/designer.log
uartfifo/designer/impl1/FIFO_top.adb
uartfifo/designer/impl1/FIFO_top.ide_des
uartfifo/designer/impl1/FIFO_top.tcl
uartfifo/designer/impl1/FIFO_top_2.adb
uartfifo/designer/impl1/FIFO_top_2.dtf/verify.log
uartfifo/designer/impl1/FIFO_top_2.ide_des
uartfifo/designer/impl1/FIFO_top_2.pdb
uartfifo/designer/impl1/FIFO_top_2.pdb.depends
uartfifo/designer/impl1/FIFO_top_2_ba.sdf
uartfifo/designer/impl1/FIFO_top_2_ba.v
uartfifo/designer/impl1/FIFO_top_2_fp/$$FlashPro_09003.L$$
uartfifo/designer/impl1/FIFO_top_2_fp/FIFO_top_2.log
uartfifo/designer/impl1/FIFO_top_2_fp/FIFO_top_2.pro
uartfifo/designer/impl1/FIFO_top_2_fp/projectData/FIFO_top_2.pdb
uartfifo/designer/impl1/syn_fifo.adb
uartfifo/designer/impl1/syn_fifo.ide_des
uartfifo/designer/impl1/syn_fifo.tcl
uartfifo/hdl/ctrl_FIFO.v
uartfifo/hdl/FIFO_top.v
uartfifo/hdl/rec.v
uartfifo/hdl/send.v
uartfifo/simulation/modelsim.ini
uartfifo/simulation/modelsim.ini.sav
uartfifo/simulation/modelsim.log
uartfifo/simulation/presynth/ctrl_@f@i@f@o/verilog.psm
uartfifo/simulation/presynth/ctrl_@f@i@f@o/_primary.dat
uartfifo/simulation/presynth/ctrl_@f@i@f@o/_primary.dbs
uartfifo/simulation/presynth/ctrl_@f@i@f@o/_primary.vhd
uartfifo/simulation/presynth/_info
uartfifo/simulation/run.do
uartfifo/simulation/vsim.wlf
uartfifo/smartgen/smartgen.aws
uartfifo/smartgen/syn_fifo/syn_fifo.cxf
uartfifo/smartgen/syn_fifo/syn_fifo.gen
uartfifo/smartgen/syn_fifo/syn_fifo.log
uartfifo/smartgen/syn_fifo/syn_fifo.v
uartfifo/smartgen/syn_fifo1/syn_fifo1.cxf
uartfifo/smartgen/syn_fifo1/syn_fifo1.gen
uartfifo/smartgen/syn_fifo1/syn_fifo1.log
uartfifo/smartgen/syn_fifo1/syn_fifo1.v
uartfifo/smartgen/syn_fifo1_work.ixf
uartfifo/smartgen/syn_fifo_work.ixf
uartfifo/synthesis/backup/FIFO_top.srr
uartfifo/synthesis/backup/FIFO_top_2.srr
uartfifo/synthesis/ctrl_FIFO.areasrr
uartfifo/synthesis/ctrl_FIFO.htm
uartfifo/synthesis/ctrl_FIFO.map
uartfifo/synthesis/ctrl_FIFO.sap
uartfifo/synthesis/ctrl_FIFO.so
uartfifo/synthesis/ctrl_FIFO.srd
uartfifo/synthesis/ctrl_FIFO.srr
uartfifo/synthesis/ctrl_FIFO_syn.prj
uartfifo/synthesis/FIFO_top.areasrr
uartfifo/synthesis/FIFO_top.htm
uartfifo/synthesis/FIFO_top.map
uartfifo/synthesis/FIFO_top.sap
uartfifo/synthesis/FIFO_top.so
uartfifo/synthesis/FIFO_top.srd
uartfifo/synthesis/FIFO_top.srr
uartfifo/synthesis/FIFO_top_1.areasrr
uartfifo/synthesis/FIFO_top_1.htm
uartfifo/synthesis/FIFO_top_1.map
uartfifo/synthesis/FIFO_top_1.sap
uartfifo/synthesis/FIFO_top_1.so
uartfifo/synthesis/FIFO_top_1.srd
uartfifo/synthesis/FIFO_top_1.srr
uartfifo/synthesis/FIFO_top_2.areasrr
uartfifo/synthesis/FIFO_top_2.edn
uartfifo/synthesis/FIFO_top_2.fse
uartfifo/synthesis/FIFO_top_2.htm
uartfifo/synthesis/FIFO_top_2.map
uartfifo/synthesis/FIFO_top_2.sap
uartfifo/synthesis/FIFO_top_2.sdf
uartfifo/synthesis/FIFO_top_2.so
uartfifo/synthesis/FIFO_top_2.srd
uartfifo/synthesis/FIFO_top_2.srm
uartfifo/synthesis/FIFO_top_2.srr
uartfifo/synthesis/FIFO_top_2.srs
uartfifo/synthesis/FIFO_top_2.tlg
uartfifo/synthesis/FIFO_top_2_sdc.sdc
uartfifo/synthesis/FIFO_top_syn.prj
uartfifo/synthesis/run_options.txt
uartfifo/synthesis/stdout.log
uartfifo/synthesis/syntmp/ctrl_FIFO.msg
uartfifo/synthesis/syntmp/ctrl_FIFO.plg
uartfifo/synthesis/syntmp/ctrl_FIFO_flink.htm
uartfifo/synthesis/syntmp/ctrl_FIFO_srr.htm
uartfifo/synthesis/syntmp/ctrl_FIFO_toc.htm
uartfifo/synthesis/syntmp/FIFO_top.msg
uartfifo/synthesis/syntmp/FIFO_top.plg
uartfifo/synthesis/syntmp/FIFO_top_1.msg
uartfifo/synthesis/syntmp/FIFO_top_1.plg
uartfifo/synthesis/syntmp/FIFO_top_1_flink.htm
uartfifo/synthesis/syntmp/FIFO_top_1_srr.htm
uartfifo/synthesis/syntmp/FIFO_top_1_toc.htm
uartfifo/synthesis/syntmp/FIFO_top_2.msg
uartfifo/synthesis/syntmp/FIFO_top_2.plg
uartfifo/synthesis/syntmp/FIFO_top_2_flink.htm
uartfifo/synthesis/syntmp/FIFO_top_2_srr.htm
uartfifo/synthesis/syntmp/FIFO_top_2_toc.htm
uartfifo/synthesis/syntmp/FIFO_top_flink.htm
uartfifo/synthesis/syntmp/FIFO_top_srr.htm
uartfifo/synthesis/syntmp/FIFO_top_toc.htm
uartfifo/synthesis/syntmp/sap.log
uartfifo/synthesis/syntmp/syn_fifo.msg
uartfifo/synthesis/syntmp/syn_fifo.plg
uartfifo/synthesis/syntmp/syn_fifo_flink.htm
uartfifo/synthesis/syntmp/syn_fifo_srr.htm
uartfifo/synthesis/syntmp/syn_fifo_toc.htm
uartfifo/synthesis/syn_fifo.areasrr
uartfifo/synthesis/syn_fifo.edn
uartfifo/synthesis/syn_fifo.fse
uartfifo/synthesis/syn_fifo.htm
uartfifo/synthesis/syn_fifo.map
uartfifo/synthesis/syn_fifo.sap
uartfifo/synthesis/syn_fifo.sdf
uartfifo/synthesis/syn_fifo.so
uartfifo/synthesis/syn_fifo.srd
uartfifo/synthesis/syn_fifo.srm
uartfifo/synthesis/syn_fifo.srr
uartfifo/synthesis/syn_fifo.srs
uartfifo/synthesis/syn_fifo.tlg
uartfifo/synthesis/syn_fifo_sdc.sdc
uartfifo/synthesis/syn_fifo_syn.prj
uartfifo/uartfifo.prj
uartfifo/viewdraw/vf/project.lst
uartfifo/viewdraw/viewdraw.ini
uartfifo/designer/impl1/FIFO_top_2_fp/projectData
uartfifo/designer/impl1/FIFO_top.dtf
uartfifo/designer/impl1/FIFO_top_2.dtf
uartfifo/designer/impl1/FIFO_top_2_fp
uartfifo/designer/impl1/simulation
uartfifo/designer/impl1/syn_fifo.dtf
uartfifo/simulation/presynth/ctrl_@f@i@f@o
uartfifo/simulation/presynt

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