4位同步二进制加法计数器的工作原理是指当时钟信号clk的上升沿到来时，且复位信号clr低电平有效时，就把计数器的状态清0。

在clr复位信号无效（即此时高电平有效）的前提下，当clk的上升沿到来时，如果计数器原态是15，计数器回到0态，否则计数器的状态将加1.

-4 synchronous binary adder counter works by the rising edge of the clock signal clk, and the reset signal CLR active low, put the state of the counter is cleared. Under the premise clr reset signal is inactive (active high), when the arrival of the rising edge of clk, if the counter original state is 15, the counter back to 0 state, or the state of the counter will be incremented by 1.