文件名称:FIR
-
所属分类:
- 标签属性:
- 上传时间:2013-05-25
-
文件大小:573kb
-
已下载:0次
-
提 供 者:
-
相关连接:无下载说明:别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容来自于网络,使用问题请自行百度
基于fpga的FIR滤波器设计,已通过modesim仿真结果正确,verilog编写-Fpga-based FIR filter design, has passed modesim simulation results are correct, verilog prepared
(系统自动生成,下载前可以参看下载内容)
下载文件列表
FIR/COFFICIENT.dat
FIR/FIR滤波器说明.pdf
FIR/quantization.m
FIR/scr/fir_filter.asv
FIR/scr/fir_filter.v
FIR/scr/signal_gen0.v
FIR/scr/tb_fir_filter.v
FIR/sim/out_data.dat
FIR/sim/signal_1m.dat
FIR/sim/signal_1m.dat.bak
FIR/sim/signal_data.dat
FIR/sim/vsim.wlf
FIR/sim/work/fir_filter/verilog.asm
FIR/sim/work/fir_filter/verilog.rw
FIR/sim/work/fir_filter/_primary.dat
FIR/sim/work/fir_filter/_primary.dbs
FIR/sim/work/fir_filter/_primary.vhd
FIR/sim/work/signal_gen0/verilog.asm
FIR/sim/work/signal_gen0/verilog.rw
FIR/sim/work/signal_gen0/_primary.dat
FIR/sim/work/signal_gen0/_primary.dbs
FIR/sim/work/signal_gen0/_primary.vhd
FIR/sim/work/tb_fir_filter/verilog.asm
FIR/sim/work/tb_fir_filter/verilog.rw
FIR/sim/work/tb_fir_filter/_primary.dat
FIR/sim/work/tb_fir_filter/_primary.dbs
FIR/sim/work/tb_fir_filter/_primary.vhd
FIR/sim/work/_info
FIR/sim/work/_temp/vlog4gf2c2
FIR/sim/work/_temp/vlog4gk2cb
FIR/sim/work/_temp/vlogdj40z3
FIR/sim/work/_temp/vloghw15yk
FIR/sim/work/_temp/vlogm8na6t
FIR/sim/work/_temp/vlogv2m9mn
FIR/sim/work/_vmake
FIR/sim/work.cr.mti
FIR/sim/work.mpf
FIR/sin_1MHz_gen.m
FIR/sim/work/fir_filter
FIR/sim/work/signal_gen0
FIR/sim/work/tb_fir_filter
FIR/sim/work/_temp
FIR/sim/work
FIR/scr
FIR/sim
FIR
FIR/FIR滤波器说明.pdf
FIR/quantization.m
FIR/scr/fir_filter.asv
FIR/scr/fir_filter.v
FIR/scr/signal_gen0.v
FIR/scr/tb_fir_filter.v
FIR/sim/out_data.dat
FIR/sim/signal_1m.dat
FIR/sim/signal_1m.dat.bak
FIR/sim/signal_data.dat
FIR/sim/vsim.wlf
FIR/sim/work/fir_filter/verilog.asm
FIR/sim/work/fir_filter/verilog.rw
FIR/sim/work/fir_filter/_primary.dat
FIR/sim/work/fir_filter/_primary.dbs
FIR/sim/work/fir_filter/_primary.vhd
FIR/sim/work/signal_gen0/verilog.asm
FIR/sim/work/signal_gen0/verilog.rw
FIR/sim/work/signal_gen0/_primary.dat
FIR/sim/work/signal_gen0/_primary.dbs
FIR/sim/work/signal_gen0/_primary.vhd
FIR/sim/work/tb_fir_filter/verilog.asm
FIR/sim/work/tb_fir_filter/verilog.rw
FIR/sim/work/tb_fir_filter/_primary.dat
FIR/sim/work/tb_fir_filter/_primary.dbs
FIR/sim/work/tb_fir_filter/_primary.vhd
FIR/sim/work/_info
FIR/sim/work/_temp/vlog4gf2c2
FIR/sim/work/_temp/vlog4gk2cb
FIR/sim/work/_temp/vlogdj40z3
FIR/sim/work/_temp/vloghw15yk
FIR/sim/work/_temp/vlogm8na6t
FIR/sim/work/_temp/vlogv2m9mn
FIR/sim/work/_vmake
FIR/sim/work.cr.mti
FIR/sim/work.mpf
FIR/sin_1MHz_gen.m
FIR/sim/work/fir_filter
FIR/sim/work/signal_gen0
FIR/sim/work/tb_fir_filter
FIR/sim/work/_temp
FIR/sim/work
FIR/scr
FIR/sim
FIR
本网站为编程资源及源代码搜集、介绍的搜索网站,版权归原作者所有! 粤ICP备11031372号
1999-2046 搜珍网 All Rights Reserved.