文件名称:clk_div_50
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- 上传时间:2013-06-29
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文件大小:351.5kb
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a kind of frequently used frequency divider as the divider factor is 50 in the code, you can change it as your wish.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
clk_div_50/my_clk_div_50.qpf
clk_div_50/my_clk_div_50_top.qsf
clk_div_50/db/my_clk_div_50_top.db_info
clk_div_50/db/my_clk_div_50_top.(0).cnf.cdb
clk_div_50/db/my_clk_div_50_top.cmp.rdb
clk_div_50/db/my_clk_div_50_top.(0).cnf.hdb
clk_div_50/db/my_clk_div_50_top.rtlv_sg_swap.cdb
clk_div_50/db/my_clk_div_50_top.lpc.txt
clk_div_50/db/my_clk_div_50_top.rtlv.hdb
clk_div_50/db/my_clk_div_50_top.lpc.html
clk_div_50/db/my_clk_div_50_top.lpc.rdb
clk_div_50/db/my_clk_div_50_top.pre_map.cdb
clk_div_50/db/my_clk_div_50.map_bb.logdb
clk_div_50/db/my_clk_div_50_top.sgdiff.cdb
clk_div_50/db/my_clk_div_50_top.sgdiff.hdb
clk_div_50/db/my_clk_div_50_top.sld_design_entry_dsc.sci
clk_div_50/db/my_clk_div_50_top.fit.qmsg
clk_div_50/db/my_clk_div_50_top.map.cdb
clk_div_50/db/logic_util_heursitic.dat
clk_div_50/db/my_clk_div_50_top.amm.cdb
clk_div_50/db/my_clk_div_50_top.rtlv_sg.cdb
clk_div_50/db/my_clk_div_50_top.cbx.xml
clk_div_50/db/my_clk_div_50_top.hif
clk_div_50/db/my_clk_div_50_top.smart_action.txt
clk_div_50/db/my_clk_div_50_top.asm.qmsg
clk_div_50/db/my_clk_div_50_top.sta.qmsg
clk_div_50/db/my_clk_div_50_top.asm.rdb
clk_div_50/db/my_clk_div_50_top.map.hdb
clk_div_50/db/my_clk_div_50_top.cmp.logdb
clk_div_50/db/my_clk_div_50_top.cmp0.ddb
clk_div_50/db/my_clk_div_50_top.cmp2.ddb
clk_div_50/db/my_clk_div_50_top.pre_map.hdb
clk_div_50/db/my_clk_div_50_top.cmp.cdb
clk_div_50/db/my_clk_div_50_top.sta_cmp.8_slow.tdb
clk_div_50/db/my_clk_div_50_top.map.bpm
clk_div_50/db/my_clk_div_50_top.cmp1.ddb
clk_div_50/db/my_clk_div_50_top.map_bb.cdb
clk_div_50/db/my_clk_div_50_top.tis_db_list.ddb
clk_div_50/db/my_clk_div_50_top.map_bb.hdb
clk_div_50/db/my_clk_div_50_top.idb.cdb
clk_div_50/db/my_clk_div_50_top.cmp.hdb
clk_div_50/db/my_clk_div_50_top.sta.rdb
clk_div_50/db/my_clk_div_50_top.asm_labs.ddb
clk_div_50/db/my_clk_div_50_top.eda.qmsg
clk_div_50/db/my_clk_div_50_top.rpp.qmsg
clk_div_50/db/my_clk_div_50_top.hier_info
clk_div_50/db/my_clk_div_50_top.sgate.rvd
clk_div_50/db/my_clk_div_50_top.sgate_sm.rvd
clk_div_50/db/prev_cmp_my_clk_div_50.qmsg
clk_div_50/db/my_clk_div_50_top.map.qmsg
clk_div_50/db/my_clk_div_50_top.sld_design_entry.sci
clk_div_50/db/my_clk_div_50_top.cmp.bpm
clk_div_50/db/my_clk_div_50_top.syn_hier_info
clk_div_50/db/my_clk_div_50_top.map.kpt
clk_div_50/db/my_clk_div_50_top.cmp_merge.kpt
clk_div_50/db/my_clk_div_50_top.cmp.kpt
clk_div_50/my_clk_div_50_top.map.summary
clk_div_50/incremental_db/compiled_partitions/my_clk_div_50_top.db_info
clk_div_50/incremental_db/compiled_partitions/my_clk_div_50_top.root_partition.map.kpt
clk_div_50/incremental_db/compiled_partitions/my_clk_div_50_top.root_partition.map.hbdb.hb_info
clk_div_50/incremental_db/compiled_partitions/my_clk_div_50_top.root_partition.map.hbdb.sig
clk_div_50/incremental_db/compiled_partitions/my_clk_div_50_top.root_partition.cmp.logdb
clk_div_50/incremental_db/compiled_partitions/my_clk_div_50_top.root_partition.cmp.kpt
clk_div_50/incremental_db/compiled_partitions/my_clk_div_50_top.root_partition.map.dpi
clk_div_50/incremental_db/compiled_partitions/my_clk_div_50_top.root_partition.map.cdb
clk_div_50/incremental_db/compiled_partitions/my_clk_div_50_top.root_partition.map.hdb
clk_div_50/incremental_db/compiled_partitions/my_clk_div_50_top.root_partition.map.hbdb.cdb
clk_div_50/incremental_db/compiled_partitions/my_clk_div_50_top.root_partition.map.hbdb.hdb
clk_div_50/incremental_db/compiled_partitions/my_clk_div_50_top.root_partition.cmp.rcfdb
clk_div_50/incremental_db/compiled_partitions/my_clk_div_50_top.root_partition.cmp.cdb
clk_div_50/incremental_db/compiled_partitions/my_clk_div_50_top.root_partition.cmp.hdb
clk_div_50/incremental_db/compiled_partitions/my_clk_div_50_top.root_partition.cmp.dfp
clk_div_50/incremental_db/README
clk_div_50/my_clk_div_50_top.pin
clk_div_50/my_clk_div_50_top.fit.smsg
clk_div_50/my_clk_div_50_top.fit.summary
clk_div_50/my_clk_div_50_top.sof
clk_div_50/my_clk_div_50_top.pof
clk_div_50/my_clk_div_50_top.done
clk_div_50/my_clk_div_50_top_nativelink_simulation.rpt
clk_div_50/simulation/modelsim/my_clk_div_50_top.vt
clk_div_50/simulation/modelsim/my_clk_div_50_top_modelsim.xrf
clk_div_50/simulation/modelsim/my_clk_div_50_top.vo
clk_div_50/simulation/modelsim/my_clk_div_50_top_fast.vo
clk_div_50/simulation/modelsim/my_clk_div_50_top_v.sdo
clk_div_50/simulation/modelsim/my_clk_div_50_top_v_fast.sdo
clk_div_50/simulation/modelsim/my_clk_div_50_top.sft
clk_div_50/simulation/modelsim/my_clk_div_50_top.vt.bak
clk_div_50/simulation/modelsim/my_clk_div_50_top_run_msim_rtl_verilog.do
clk_div_50/simulation/modelsim/vsim.wlf
clk_div_50/simulation/modelsim/my_clk_div_50_top_run_msim_rtl_verilog.do.bak
clk_div_50/simulation/modelsim/my_clk_div_50_top_run_msim_rtl_verilog.do.bak1
clk_div_50/simulation/modelsim/my_clk_div_50_top_run_msim_rtl_verilog.do.bak2
clk_div_50/simulation/modelsim/msim_transcript
clk_div_50/simulation/modelsim/rtl_work/_info
clk_div_50/simulation/modelsim/rtl_work/_vmake
clk_div_50/simulation/modelsim/rtl_work/my_clk_div_50_top/_primary.vhd
clk_div_50/simulation/modelsim/rtl_work/my_clk_div_50_top/verilog.psm
clk_div_50/simulation/modelsi
clk_div_50/my_clk_div_50_top.qsf
clk_div_50/db/my_clk_div_50_top.db_info
clk_div_50/db/my_clk_div_50_top.(0).cnf.cdb
clk_div_50/db/my_clk_div_50_top.cmp.rdb
clk_div_50/db/my_clk_div_50_top.(0).cnf.hdb
clk_div_50/db/my_clk_div_50_top.rtlv_sg_swap.cdb
clk_div_50/db/my_clk_div_50_top.lpc.txt
clk_div_50/db/my_clk_div_50_top.rtlv.hdb
clk_div_50/db/my_clk_div_50_top.lpc.html
clk_div_50/db/my_clk_div_50_top.lpc.rdb
clk_div_50/db/my_clk_div_50_top.pre_map.cdb
clk_div_50/db/my_clk_div_50.map_bb.logdb
clk_div_50/db/my_clk_div_50_top.sgdiff.cdb
clk_div_50/db/my_clk_div_50_top.sgdiff.hdb
clk_div_50/db/my_clk_div_50_top.sld_design_entry_dsc.sci
clk_div_50/db/my_clk_div_50_top.fit.qmsg
clk_div_50/db/my_clk_div_50_top.map.cdb
clk_div_50/db/logic_util_heursitic.dat
clk_div_50/db/my_clk_div_50_top.amm.cdb
clk_div_50/db/my_clk_div_50_top.rtlv_sg.cdb
clk_div_50/db/my_clk_div_50_top.cbx.xml
clk_div_50/db/my_clk_div_50_top.hif
clk_div_50/db/my_clk_div_50_top.smart_action.txt
clk_div_50/db/my_clk_div_50_top.asm.qmsg
clk_div_50/db/my_clk_div_50_top.sta.qmsg
clk_div_50/db/my_clk_div_50_top.asm.rdb
clk_div_50/db/my_clk_div_50_top.map.hdb
clk_div_50/db/my_clk_div_50_top.cmp.logdb
clk_div_50/db/my_clk_div_50_top.cmp0.ddb
clk_div_50/db/my_clk_div_50_top.cmp2.ddb
clk_div_50/db/my_clk_div_50_top.pre_map.hdb
clk_div_50/db/my_clk_div_50_top.cmp.cdb
clk_div_50/db/my_clk_div_50_top.sta_cmp.8_slow.tdb
clk_div_50/db/my_clk_div_50_top.map.bpm
clk_div_50/db/my_clk_div_50_top.cmp1.ddb
clk_div_50/db/my_clk_div_50_top.map_bb.cdb
clk_div_50/db/my_clk_div_50_top.tis_db_list.ddb
clk_div_50/db/my_clk_div_50_top.map_bb.hdb
clk_div_50/db/my_clk_div_50_top.idb.cdb
clk_div_50/db/my_clk_div_50_top.cmp.hdb
clk_div_50/db/my_clk_div_50_top.sta.rdb
clk_div_50/db/my_clk_div_50_top.asm_labs.ddb
clk_div_50/db/my_clk_div_50_top.eda.qmsg
clk_div_50/db/my_clk_div_50_top.rpp.qmsg
clk_div_50/db/my_clk_div_50_top.hier_info
clk_div_50/db/my_clk_div_50_top.sgate.rvd
clk_div_50/db/my_clk_div_50_top.sgate_sm.rvd
clk_div_50/db/prev_cmp_my_clk_div_50.qmsg
clk_div_50/db/my_clk_div_50_top.map.qmsg
clk_div_50/db/my_clk_div_50_top.sld_design_entry.sci
clk_div_50/db/my_clk_div_50_top.cmp.bpm
clk_div_50/db/my_clk_div_50_top.syn_hier_info
clk_div_50/db/my_clk_div_50_top.map.kpt
clk_div_50/db/my_clk_div_50_top.cmp_merge.kpt
clk_div_50/db/my_clk_div_50_top.cmp.kpt
clk_div_50/my_clk_div_50_top.map.summary
clk_div_50/incremental_db/compiled_partitions/my_clk_div_50_top.db_info
clk_div_50/incremental_db/compiled_partitions/my_clk_div_50_top.root_partition.map.kpt
clk_div_50/incremental_db/compiled_partitions/my_clk_div_50_top.root_partition.map.hbdb.hb_info
clk_div_50/incremental_db/compiled_partitions/my_clk_div_50_top.root_partition.map.hbdb.sig
clk_div_50/incremental_db/compiled_partitions/my_clk_div_50_top.root_partition.cmp.logdb
clk_div_50/incremental_db/compiled_partitions/my_clk_div_50_top.root_partition.cmp.kpt
clk_div_50/incremental_db/compiled_partitions/my_clk_div_50_top.root_partition.map.dpi
clk_div_50/incremental_db/compiled_partitions/my_clk_div_50_top.root_partition.map.cdb
clk_div_50/incremental_db/compiled_partitions/my_clk_div_50_top.root_partition.map.hdb
clk_div_50/incremental_db/compiled_partitions/my_clk_div_50_top.root_partition.map.hbdb.cdb
clk_div_50/incremental_db/compiled_partitions/my_clk_div_50_top.root_partition.map.hbdb.hdb
clk_div_50/incremental_db/compiled_partitions/my_clk_div_50_top.root_partition.cmp.rcfdb
clk_div_50/incremental_db/compiled_partitions/my_clk_div_50_top.root_partition.cmp.cdb
clk_div_50/incremental_db/compiled_partitions/my_clk_div_50_top.root_partition.cmp.hdb
clk_div_50/incremental_db/compiled_partitions/my_clk_div_50_top.root_partition.cmp.dfp
clk_div_50/incremental_db/README
clk_div_50/my_clk_div_50_top.pin
clk_div_50/my_clk_div_50_top.fit.smsg
clk_div_50/my_clk_div_50_top.fit.summary
clk_div_50/my_clk_div_50_top.sof
clk_div_50/my_clk_div_50_top.pof
clk_div_50/my_clk_div_50_top.done
clk_div_50/my_clk_div_50_top_nativelink_simulation.rpt
clk_div_50/simulation/modelsim/my_clk_div_50_top.vt
clk_div_50/simulation/modelsim/my_clk_div_50_top_modelsim.xrf
clk_div_50/simulation/modelsim/my_clk_div_50_top.vo
clk_div_50/simulation/modelsim/my_clk_div_50_top_fast.vo
clk_div_50/simulation/modelsim/my_clk_div_50_top_v.sdo
clk_div_50/simulation/modelsim/my_clk_div_50_top_v_fast.sdo
clk_div_50/simulation/modelsim/my_clk_div_50_top.sft
clk_div_50/simulation/modelsim/my_clk_div_50_top.vt.bak
clk_div_50/simulation/modelsim/my_clk_div_50_top_run_msim_rtl_verilog.do
clk_div_50/simulation/modelsim/vsim.wlf
clk_div_50/simulation/modelsim/my_clk_div_50_top_run_msim_rtl_verilog.do.bak
clk_div_50/simulation/modelsim/my_clk_div_50_top_run_msim_rtl_verilog.do.bak1
clk_div_50/simulation/modelsim/my_clk_div_50_top_run_msim_rtl_verilog.do.bak2
clk_div_50/simulation/modelsim/msim_transcript
clk_div_50/simulation/modelsim/rtl_work/_info
clk_div_50/simulation/modelsim/rtl_work/_vmake
clk_div_50/simulation/modelsim/rtl_work/my_clk_div_50_top/_primary.vhd
clk_div_50/simulation/modelsim/rtl_work/my_clk_div_50_top/verilog.psm
clk_div_50/simulation/modelsi
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