actelIP核 的fircore

Core Generator

– Executable File Outputs Run-Time Library (RTL)

Code and Testbench Based on Input Parameters

– Self-Checking – Executable Tests Generated

Output against Algorithm

• Distributed Arithmetic (DA) Algorithm

– Multiplier-Free Computation

– Low Cost

– Optimized for Actel FPGAs

• Folding Architecture to Minimize Design Size

– Serialized Computation when System Clock

Rate is Faster than the Data Sample Rate

• Efficient Structure Using Embedded RAMs

– Lookup Tables Utilize Embedded RAMs

• On-Chip DA Lookup Table Generator for FPGA

with Embedded RAMs

• Embedded RAMs Initialized as DA Lookup Table

• DA Lookup Table ROM Synthesis for FPGA without

Embedded RAMs

• Multiple DA lookup Tables to Split Large Number

of Taps

• Actel FPGA-Optimized RTL Code

• Supports 2 to 128 Taps

• 1- to 32-Bit Input Data and Coefficient Precision-actelIPcore fircore

Core Generator

– Executable File Outputs Run-Time Library (RTL)

Code and Testbench Based on Input Parameters

– Self-Checking – Executable Tests Generated

Output against Algorithm

•　Distributed Arithmetic (DA) Algorithm

– Multiplier-Free Computation

– Low Cost

– Optimized for Actel FPGAs

•　Folding Architecture to Minimize Design Size

– Serialized Computation when System Clock

Rate is Faster than the Data Sample Rate

•　Efficient Structure Using Embedded RAMs

– Lookup Tables Utilize Embedded RAMs

•　On-Chip DA Lookup Table Generator for FPGA

with Embedded RAMs

•　Embedded RAMs Initialized as DA Lookup Table

•　DA Lookup Table ROM Synthesis for FPGA without

Embedded RAMs

•　Multiple DA lookup Tables to Split Large Number

of Taps

•　Actel FPGA-Optimized RTL Code

•　Supports 2 to 128 Taps

•　1- to 32-Bit Input Data and Coefficient Precision