文件名称:i2c
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- 上传时间:2013-09-14
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文件大小:713.21kb
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iic总线编写例,可以借鉴使用,编程Verilog语言。-iic bus prepare cases, you can learn to use Verilog programming language.
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下载文件列表
i2c/
i2c/bench/
i2c/bench/CVS/
i2c/bench/CVS/Entries
i2c/bench/CVS/Entries.Extra
i2c/bench/CVS/Repository
i2c/bench/CVS/Root
i2c/bench/CVS/Template
i2c/bench/verilog/
i2c/bench/verilog/CVS/
i2c/bench/verilog/CVS/Entries
i2c/bench/verilog/CVS/Entries.Extra
i2c/bench/verilog/CVS/Repository
i2c/bench/verilog/CVS/Root
i2c/bench/verilog/CVS/Template
i2c/bench/verilog/i2c_slave_model.v
i2c/bench/verilog/spi_slave_model.v
i2c/bench/verilog/tst_bench_top.v
i2c/bench/verilog/wb_master_model.v
i2c/CVS/
i2c/CVS/Entries
i2c/CVS/Entries.Extra
i2c/CVS/Repository
i2c/CVS/Root
i2c/CVS/Template
i2c/doc/
i2c/doc/CVS/
i2c/doc/CVS/Entries
i2c/doc/CVS/Entries.Extra
i2c/doc/CVS/Repository
i2c/doc/CVS/Root
i2c/doc/CVS/Template
i2c/doc/i2c_specs.pdf
i2c/doc/src/
i2c/doc/src/CVS/
i2c/doc/src/CVS/Entries
i2c/doc/src/CVS/Entries.Extra
i2c/doc/src/CVS/Repository
i2c/doc/src/CVS/Root
i2c/doc/src/CVS/Template
i2c/doc/src/I2C_specs.doc
i2c/rtl/
i2c/rtl/CVS/
i2c/rtl/CVS/Entries
i2c/rtl/CVS/Entries.Extra
i2c/rtl/CVS/Repository
i2c/rtl/CVS/Root
i2c/rtl/CVS/Template
i2c/rtl/verilog/
i2c/rtl/verilog/CVS/
i2c/rtl/verilog/CVS/Entries
i2c/rtl/verilog/CVS/Entries.Extra
i2c/rtl/verilog/CVS/Repository
i2c/rtl/verilog/CVS/Root
i2c/rtl/verilog/CVS/Template
i2c/rtl/verilog/i2c_master_bit_ctrl.v
i2c/rtl/verilog/i2c_master_byte_ctrl.v
i2c/rtl/verilog/i2c_master_defines.v
i2c/rtl/verilog/i2c_master_top.v
i2c/rtl/verilog/timescale.v
i2c/rtl/vhdl/
i2c/rtl/vhdl/CVS/
i2c/rtl/vhdl/CVS/Entries
i2c/rtl/vhdl/CVS/Entries.Extra
i2c/rtl/vhdl/CVS/Repository
i2c/rtl/vhdl/CVS/Root
i2c/rtl/vhdl/CVS/Template
i2c/rtl/vhdl/I2C.VHD
i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd
i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd
i2c/rtl/vhdl/i2c_master_top.vhd
i2c/rtl/vhdl/readme
i2c/rtl/vhdl/tst_ds1621.vhd
i2c/sim/
i2c/sim/CVS/
i2c/sim/CVS/Entries
i2c/sim/CVS/Entries.Extra
i2c/sim/CVS/Repository
i2c/sim/CVS/Root
i2c/sim/CVS/Template
i2c/sim/i2c_verilog/
i2c/sim/i2c_verilog/CVS/
i2c/sim/i2c_verilog/CVS/Entries
i2c/sim/i2c_verilog/CVS/Entries.Extra
i2c/sim/i2c_verilog/CVS/Repository
i2c/sim/i2c_verilog/CVS/Root
i2c/sim/i2c_verilog/CVS/Template
i2c/sim/i2c_verilog/run/
i2c/sim/i2c_verilog/run/bench.vcd
i2c/sim/i2c_verilog/run/CVS/
i2c/sim/i2c_verilog/run/CVS/Entries
i2c/sim/i2c_verilog/run/CVS/Entries.Extra
i2c/sim/i2c_verilog/run/CVS/Repository
i2c/sim/i2c_verilog/run/CVS/Root
i2c/sim/i2c_verilog/run/CVS/Template
i2c/sim/i2c_verilog/run/ncverilog.key
i2c/sim/i2c_verilog/run/ncverilog.log
i2c/sim/i2c_verilog/run/run
i2c/software/
i2c/software/CVS/
i2c/software/CVS/Entries
i2c/software/CVS/Entries.Extra
i2c/software/CVS/Repository
i2c/software/CVS/Root
i2c/software/CVS/Template
i2c/software/include/
i2c/software/include/CVS/
i2c/software/include/CVS/Entries
i2c/software/include/CVS/Entries.Extra
i2c/software/include/CVS/Repository
i2c/software/include/CVS/Root
i2c/software/include/CVS/Template
i2c/software/include/oc_i2c_master.h
i2c/bench/
i2c/bench/CVS/
i2c/bench/CVS/Entries
i2c/bench/CVS/Entries.Extra
i2c/bench/CVS/Repository
i2c/bench/CVS/Root
i2c/bench/CVS/Template
i2c/bench/verilog/
i2c/bench/verilog/CVS/
i2c/bench/verilog/CVS/Entries
i2c/bench/verilog/CVS/Entries.Extra
i2c/bench/verilog/CVS/Repository
i2c/bench/verilog/CVS/Root
i2c/bench/verilog/CVS/Template
i2c/bench/verilog/i2c_slave_model.v
i2c/bench/verilog/spi_slave_model.v
i2c/bench/verilog/tst_bench_top.v
i2c/bench/verilog/wb_master_model.v
i2c/CVS/
i2c/CVS/Entries
i2c/CVS/Entries.Extra
i2c/CVS/Repository
i2c/CVS/Root
i2c/CVS/Template
i2c/doc/
i2c/doc/CVS/
i2c/doc/CVS/Entries
i2c/doc/CVS/Entries.Extra
i2c/doc/CVS/Repository
i2c/doc/CVS/Root
i2c/doc/CVS/Template
i2c/doc/i2c_specs.pdf
i2c/doc/src/
i2c/doc/src/CVS/
i2c/doc/src/CVS/Entries
i2c/doc/src/CVS/Entries.Extra
i2c/doc/src/CVS/Repository
i2c/doc/src/CVS/Root
i2c/doc/src/CVS/Template
i2c/doc/src/I2C_specs.doc
i2c/rtl/
i2c/rtl/CVS/
i2c/rtl/CVS/Entries
i2c/rtl/CVS/Entries.Extra
i2c/rtl/CVS/Repository
i2c/rtl/CVS/Root
i2c/rtl/CVS/Template
i2c/rtl/verilog/
i2c/rtl/verilog/CVS/
i2c/rtl/verilog/CVS/Entries
i2c/rtl/verilog/CVS/Entries.Extra
i2c/rtl/verilog/CVS/Repository
i2c/rtl/verilog/CVS/Root
i2c/rtl/verilog/CVS/Template
i2c/rtl/verilog/i2c_master_bit_ctrl.v
i2c/rtl/verilog/i2c_master_byte_ctrl.v
i2c/rtl/verilog/i2c_master_defines.v
i2c/rtl/verilog/i2c_master_top.v
i2c/rtl/verilog/timescale.v
i2c/rtl/vhdl/
i2c/rtl/vhdl/CVS/
i2c/rtl/vhdl/CVS/Entries
i2c/rtl/vhdl/CVS/Entries.Extra
i2c/rtl/vhdl/CVS/Repository
i2c/rtl/vhdl/CVS/Root
i2c/rtl/vhdl/CVS/Template
i2c/rtl/vhdl/I2C.VHD
i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd
i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd
i2c/rtl/vhdl/i2c_master_top.vhd
i2c/rtl/vhdl/readme
i2c/rtl/vhdl/tst_ds1621.vhd
i2c/sim/
i2c/sim/CVS/
i2c/sim/CVS/Entries
i2c/sim/CVS/Entries.Extra
i2c/sim/CVS/Repository
i2c/sim/CVS/Root
i2c/sim/CVS/Template
i2c/sim/i2c_verilog/
i2c/sim/i2c_verilog/CVS/
i2c/sim/i2c_verilog/CVS/Entries
i2c/sim/i2c_verilog/CVS/Entries.Extra
i2c/sim/i2c_verilog/CVS/Repository
i2c/sim/i2c_verilog/CVS/Root
i2c/sim/i2c_verilog/CVS/Template
i2c/sim/i2c_verilog/run/
i2c/sim/i2c_verilog/run/bench.vcd
i2c/sim/i2c_verilog/run/CVS/
i2c/sim/i2c_verilog/run/CVS/Entries
i2c/sim/i2c_verilog/run/CVS/Entries.Extra
i2c/sim/i2c_verilog/run/CVS/Repository
i2c/sim/i2c_verilog/run/CVS/Root
i2c/sim/i2c_verilog/run/CVS/Template
i2c/sim/i2c_verilog/run/ncverilog.key
i2c/sim/i2c_verilog/run/ncverilog.log
i2c/sim/i2c_verilog/run/run
i2c/software/
i2c/software/CVS/
i2c/software/CVS/Entries
i2c/software/CVS/Entries.Extra
i2c/software/CVS/Repository
i2c/software/CVS/Root
i2c/software/CVS/Template
i2c/software/include/
i2c/software/include/CVS/
i2c/software/include/CVS/Entries
i2c/software/include/CVS/Entries.Extra
i2c/software/include/CVS/Repository
i2c/software/include/CVS/Root
i2c/software/include/CVS/Template
i2c/software/include/oc_i2c_master.h
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