Leakage power dissipation becomes a dominant

component in operation power in nanometer devices. This paper

describes a design methodology to implement runtime power

gating in a fine-grained manner. We propose an approach to use

sleep signals that are not off-chip but are extracted locally within

the design. By utilizing enable signals in a gated clock design, we

automatically partition the design into domains. We then choose

the domains that will achieve the gain in energy savings by

considering dynamic energy overhead due to turning on/off power

switches.