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文件名称:verilog_prj_seq

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    2013-09-23
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    1.57mb
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序列检测器,检测序列“11010”,verilog HDL代码。-Sequence detector, detection sequence "11010", verilog HDL code.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

verilog_prj_seq/db/prev_cmp_verilog_prj_seq.asm.qmsg
verilog_prj_seq/db/prev_cmp_verilog_prj_seq.eda.qmsg
verilog_prj_seq/db/prev_cmp_verilog_prj_seq.fit.qmsg
verilog_prj_seq/db/prev_cmp_verilog_prj_seq.map.qmsg
verilog_prj_seq/db/prev_cmp_verilog_prj_seq.qmsg
verilog_prj_seq/db/prev_cmp_verilog_prj_seq.tan.qmsg
verilog_prj_seq/db/verilog_prj_seq.(0).cnf.cdb
verilog_prj_seq/db/verilog_prj_seq.(0).cnf.hdb
verilog_prj_seq/db/verilog_prj_seq.asm.qmsg
verilog_prj_seq/db/verilog_prj_seq.asm_labs.ddb
verilog_prj_seq/db/verilog_prj_seq.cbx.xml
verilog_prj_seq/db/verilog_prj_seq.cmp.cdb
verilog_prj_seq/db/verilog_prj_seq.cmp.hdb
verilog_prj_seq/db/verilog_prj_seq.cmp.kpt
verilog_prj_seq/db/verilog_prj_seq.cmp.logdb
verilog_prj_seq/db/verilog_prj_seq.cmp.rdb
verilog_prj_seq/db/verilog_prj_seq.cmp.tdb
verilog_prj_seq/db/verilog_prj_seq.cmp0.ddb
verilog_prj_seq/db/verilog_prj_seq.db_info
verilog_prj_seq/db/verilog_prj_seq.eco.cdb
verilog_prj_seq/db/verilog_prj_seq.eda.qmsg
verilog_prj_seq/db/verilog_prj_seq.fit.qmsg
verilog_prj_seq/db/verilog_prj_seq.hier_info
verilog_prj_seq/db/verilog_prj_seq.hif
verilog_prj_seq/db/verilog_prj_seq.lpc.html
verilog_prj_seq/db/verilog_prj_seq.lpc.rdb
verilog_prj_seq/db/verilog_prj_seq.lpc.txt
verilog_prj_seq/db/verilog_prj_seq.map.cdb
verilog_prj_seq/db/verilog_prj_seq.map.hdb
verilog_prj_seq/db/verilog_prj_seq.map.logdb
verilog_prj_seq/db/verilog_prj_seq.map.qmsg
verilog_prj_seq/db/verilog_prj_seq.pre_map.cdb
verilog_prj_seq/db/verilog_prj_seq.pre_map.hdb
verilog_prj_seq/db/verilog_prj_seq.rtlv.hdb
verilog_prj_seq/db/verilog_prj_seq.rtlv_sg.cdb
verilog_prj_seq/db/verilog_prj_seq.rtlv_sg_swap.cdb
verilog_prj_seq/db/verilog_prj_seq.sgdiff.cdb
verilog_prj_seq/db/verilog_prj_seq.sgdiff.hdb
verilog_prj_seq/db/verilog_prj_seq.sld_design_entry.sci
verilog_prj_seq/db/verilog_prj_seq.sld_design_entry_dsc.sci
verilog_prj_seq/db/verilog_prj_seq.smp_dump.txt
verilog_prj_seq/db/verilog_prj_seq.syn_hier_info
verilog_prj_seq/db/verilog_prj_seq.tan.qmsg
verilog_prj_seq/db/verilog_prj_seq.tis_db_list.ddb
verilog_prj_seq/db/verilog_prj_seq.tmw_info
verilog_prj_seq/incremental_db/compiled_partitions/verilog_prj_seq.root_partition.map.kpt
verilog_prj_seq/incremental_db/README
verilog_prj_seq/simulation/modelsim/modelsim.ini
verilog_prj_seq/simulation/modelsim/msim_transcript
verilog_prj_seq/simulation/modelsim/rtl_work/@_opt/vopt0jfc6w
verilog_prj_seq/simulation/modelsim/rtl_work/@_opt/vopt1nkfzt
verilog_prj_seq/simulation/modelsim/rtl_work/@_opt/vopt43596w
verilog_prj_seq/simulation/modelsim/rtl_work/@_opt/vopt46aczt
verilog_prj_seq/simulation/modelsim/rtl_work/@_opt/vopt7jt66w
verilog_prj_seq/simulation/modelsim/rtl_work/@_opt/vopt8nz8zt
verilog_prj_seq/simulation/modelsim/rtl_work/@_opt/voptb3g36w
verilog_prj_seq/simulation/modelsim/rtl_work/@_opt/voptc5j84w
verilog_prj_seq/simulation/modelsim/rtl_work/@_opt/voptf59zzt
verilog_prj_seq/simulation/modelsim/rtl_work/@_opt/voptfm854w
verilog_prj_seq/simulation/modelsim/rtl_work/@_opt/voptiiss6w
verilog_prj_seq/simulation/modelsim/rtl_work/@_opt/voptimywzt
verilog_prj_seq/simulation/modelsim/rtl_work/@_opt/voptj5y14w
verilog_prj_seq/simulation/modelsim/rtl_work/@_opt/voptm2fn6w
verilog_prj_seq/simulation/modelsim/rtl_work/@_opt/voptnmrsfs
verilog_prj_seq/simulation/modelsim/rtl_work/@_opt/vopts2mjnn
verilog_prj_seq/simulation/modelsim/rtl_work/@_opt/voptx3cimn
verilog_prj_seq/simulation/modelsim/rtl_work/@_opt/voptxiagnn
verilog_prj_seq/simulation/modelsim/rtl_work/@_opt/_deps
verilog_prj_seq/simulation/modelsim/rtl_work/verilog_prj_seq/_primary.dat
verilog_prj_seq/simulation/modelsim/rtl_work/verilog_prj_seq/_primary.dbs
verilog_prj_seq/simulation/modelsim/rtl_work/verilog_prj_seq/_primary.vhd
verilog_prj_seq/simulation/modelsim/rtl_work/verilog_prj_seq_test/_primary.dat
verilog_prj_seq/simulation/modelsim/rtl_work/verilog_prj_seq_test/_primary.dbs
verilog_prj_seq/simulation/modelsim/rtl_work/verilog_prj_seq_test/_primary.vhd
verilog_prj_seq/simulation/modelsim/rtl_work/_info
verilog_prj_seq/simulation/modelsim/rtl_work/_vmake
verilog_prj_seq/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dat
verilog_prj_seq/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dbs
verilog_prj_seq/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.vhd
verilog_prj_seq/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.dat
verilog_prj_seq/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.dbs
verilog_prj_seq/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.vhd
verilog_prj_seq/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.dat
verilog_prj_seq/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.dbs
verilog_prj_seq/simulation/modelsim/verilog_libs/altera_mf_ver/@

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