文件名称:ethernet.tar
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verilog写的以太网硬件模型,使用xilinx FPGA,ieee802.3ae-an ethernet model in Verilog,using a Xilinx FPGA,and the function:IEEE 802.3ae Media Access Control (MAC) Parameters, Physical Layers,
and Management Parameters for 10 Gb/s Operation
and Management Parameters for 10 Gb/s Operation
(系统自动生成,下载前可以参看下载内容)
下载文件列表
ethmac10g/
ethmac10g/branches/
ethmac10g/tags/
ethmac10g/tags/V10/
ethmac10g/tags/V10/rxReceiveEngine.v
ethmac10g/tags/V10/rxtest.v
ethmac10g/tags/V10/rxFrameDepart.v
ethmac10g/tags/V10/counter.v
ethmac10g/tags/V10/10G Ethernet MAC System Design.doc
ethmac10g/tags/V10/bench/
ethmac10g/tags/V10/bench/TransmitTop.mpf
ethmac10g/tags/V10/bench/rxtest.v
ethmac10g/tags/V10/bench/debug.do
ethmac10g/tags/V10/bench/debug_large.do
ethmac10g/tags/V10/bench/TransmitTop_tb.v
ethmac10g/tags/V10/bench/TransmitTop_CRC_tb.v
ethmac10g/tags/V10/bench/TransmitTop_pause_tb.v
ethmac10g/tags/V10/bench/TransmitTop_min_frame_tb.v
ethmac10g/tags/V10/bench/debug_pause.do
ethmac10g/tags/V10/rxdatafifo.v
ethmac10g/tags/V10/rxcntrlfifo.v
ethmac10g/tags/V10/rxRSIO.v
ethmac10g/tags/V10/M2_1E.v
ethmac10g/tags/V10/rxFIFOMgnt.v
ethmac10g/tags/V10/rxRSLayer.v
ethmac10g/tags/V10/rxLenTypChecker.v
ethmac10g/tags/V10/rtl/
ethmac10g/tags/V10/rtl/verilog/
ethmac10g/tags/V10/rtl/verilog/rx_engine/
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxReceiveEngine.ucf
ethmac10g/tags/V10/rtl/verilog/rx_engine/timescale.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/CRC32_D8.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxReceiveEngine.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/counter.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/xgiga_define.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxCRC.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxdatafifo.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxcntrlfifo.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxRSIO.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxcntrlfifo.xco
ethmac10g/tags/V10/rtl/verilog/rx_engine/dcm0.xaw
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxRSLayer.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxdatafifo.xco
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxLenTypChecker.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxDAchecker.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/CRC32_D64.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxClkgen.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxNumCounter.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxDataPath.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxStatModule.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxStateMachine.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxLinkFaultState.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/dcm0.v
ethmac10g/tags/V10/rtl/verilog/tx_engine/
ethmac10g/tags/V10/rtl/verilog/tx_engine/CRC32_D8.v
ethmac10g/tags/V10/rtl/verilog/tx_engine/byte_counter.v
ethmac10g/tags/V10/rtl/verilog/tx_engine/ack_counter.v
ethmac10g/tags/V10/rtl/verilog/tx_engine/CRC32_D64.v
ethmac10g/tags/V10/rtl/verilog/tx_engine/TransmitTop.v
ethmac10g/tags/V10/10gmac.ise
ethmac10g/tags/V10/doc/
ethmac10g/tags/V10/doc/transmit.pdf
ethmac10g/tags/V10/rxDAchecker.v
ethmac10g/tags/V10/10gmac.ise_ISE_Backup
ethmac10g/tags/V10/rxClkgen.v
ethmac10g/tags/V10/rxNumCounter.v
ethmac10g/tags/V10/M8_1E.v
ethmac10g/tags/V10/rxStateMachine.v
ethmac10g/tags/V10/rxLinkFaultState.v
ethmac10g/tags/V10/dcm0.v
ethmac10g/web_uploads/
ethmac10g/trunk/
ethmac10g/trunk/bench/
ethmac10g/trunk/bench/TransmitTop.mpf
ethmac10g/trunk/bench/debug.do
ethmac10g/trunk/bench/debug_large.do
ethmac10g/trunk/bench/Receive_tb.v
ethmac10g/trunk/bench/TransmitTop_tb.v
ethmac10g/trunk/bench/TransmitTop_CRC_tb.v
ethmac10g/trunk/bench/management_tb.v
ethmac10g/trunk/bench/TransmitTop_pause_tb.v
ethmac10g/trunk/bench/TransmitTop_min_frame_tb.v
ethmac10g/trunk/bench/debug_pause.do
ethmac10g/trunk/rtl/
ethmac10g/trunk/rtl/verilog/
ethmac10g/trunk/rtl/verilog/rx_engine/
ethmac10g/trunk/rtl/verilog/rx_engine/rxReceiveEngine.ucf
ethmac10g/trunk/rtl/verilog/rx_engine/timescale.v
ethmac10g/trunk/rtl/verilog/rx_engine/CRC32_D8.v
ethmac10g/trunk/rtl/verilog/rx_engine/SwitchAsyncFIFO.v
ethmac10g/trunk/rtl/verilog/rx_engine/rxReceiveEngine.v
ethmac10g/trunk/rtl/verilog/rx_engine/counter.v
ethmac10g/trunk/rtl/verilog/rx_engine/xgiga_define.v
ethmac10g/trunk/rtl/verilog/rx_engine/rxCRC.v
ethmac10g/trunk/rtl/verilog/rx_engine/SwitchSyncFIFO.v
ethmac10g/trunk/rtl/verilog/rx_engine/rxRSIO.v
ethmac10g/trunk/rtl/verilog/rx_engine/rxRSLayer.v
ethmac10g/trunk/rtl/verilog/rx_engine/rxLenTypChecker.v
ethmac10g/trunk/rtl/verilog/rx_engine/rxDAchecker.v
ethmac10g/trunk/rtl/verilog/rx_engine/CRC32_D64.v
ethmac10g/trunk/rtl/verilog/rx_engine/rxClkgen.v
ethmac10g/trunk/rtl/verilog/rx_engine/rxNumCounter.v
ethmac10g/trunk/rtl/verilog/rx_engine/rxDataPath.v
ethmac10g/trunk/rtl/verilog/rx_engine/rxStatModule.v
ethmac10g/trunk/rtl/verilog/rx_engine/rxStateMachine.v
ethmac10g/trunk/rtl/verilog/rx_engine/rxLinkFaultState.v
ethmac10g/trunk/rtl/verilog/mgmt/
ethmac10g/trunk/rtl/verilog/mgmt/management_top.v
ethmac10g/trunk/rtl/verilog/mgmt/manage_registers.v
ethmac10g/trunk/rtl/verilog/mgmt/mdio.v
ethmac10g/trunk/rtl/verilog/tx_engine/
ethmac10g/trunk/rtl/verilog/tx_engine/CRC32_D8.v
ethmac10g/trunk/rtl/verilog/tx_engine/byte_counter.v
ethmac10g/trunk/rtl/verilog/tx_engine/ack_counter.v
ethmac10g/trunk/rtl/verilog/tx_engine/CRC32_D64.v
ethmac10g/trunk/rtl/verilog/tx_engine/TransmitTop.v
ethmac10g/trunk/doc/
ethmac10g/trunk/doc/transmit.pdf
ethmac10g/trunk/doc/Receive.pdf
ethmac10g/trunk/doc/managemen
ethmac10g/branches/
ethmac10g/tags/
ethmac10g/tags/V10/
ethmac10g/tags/V10/rxReceiveEngine.v
ethmac10g/tags/V10/rxtest.v
ethmac10g/tags/V10/rxFrameDepart.v
ethmac10g/tags/V10/counter.v
ethmac10g/tags/V10/10G Ethernet MAC System Design.doc
ethmac10g/tags/V10/bench/
ethmac10g/tags/V10/bench/TransmitTop.mpf
ethmac10g/tags/V10/bench/rxtest.v
ethmac10g/tags/V10/bench/debug.do
ethmac10g/tags/V10/bench/debug_large.do
ethmac10g/tags/V10/bench/TransmitTop_tb.v
ethmac10g/tags/V10/bench/TransmitTop_CRC_tb.v
ethmac10g/tags/V10/bench/TransmitTop_pause_tb.v
ethmac10g/tags/V10/bench/TransmitTop_min_frame_tb.v
ethmac10g/tags/V10/bench/debug_pause.do
ethmac10g/tags/V10/rxdatafifo.v
ethmac10g/tags/V10/rxcntrlfifo.v
ethmac10g/tags/V10/rxRSIO.v
ethmac10g/tags/V10/M2_1E.v
ethmac10g/tags/V10/rxFIFOMgnt.v
ethmac10g/tags/V10/rxRSLayer.v
ethmac10g/tags/V10/rxLenTypChecker.v
ethmac10g/tags/V10/rtl/
ethmac10g/tags/V10/rtl/verilog/
ethmac10g/tags/V10/rtl/verilog/rx_engine/
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxReceiveEngine.ucf
ethmac10g/tags/V10/rtl/verilog/rx_engine/timescale.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/CRC32_D8.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxReceiveEngine.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/counter.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/xgiga_define.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxCRC.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxdatafifo.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxcntrlfifo.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxRSIO.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxcntrlfifo.xco
ethmac10g/tags/V10/rtl/verilog/rx_engine/dcm0.xaw
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxRSLayer.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxdatafifo.xco
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxLenTypChecker.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxDAchecker.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/CRC32_D64.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxClkgen.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxNumCounter.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxDataPath.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxStatModule.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxStateMachine.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/rxLinkFaultState.v
ethmac10g/tags/V10/rtl/verilog/rx_engine/dcm0.v
ethmac10g/tags/V10/rtl/verilog/tx_engine/
ethmac10g/tags/V10/rtl/verilog/tx_engine/CRC32_D8.v
ethmac10g/tags/V10/rtl/verilog/tx_engine/byte_counter.v
ethmac10g/tags/V10/rtl/verilog/tx_engine/ack_counter.v
ethmac10g/tags/V10/rtl/verilog/tx_engine/CRC32_D64.v
ethmac10g/tags/V10/rtl/verilog/tx_engine/TransmitTop.v
ethmac10g/tags/V10/10gmac.ise
ethmac10g/tags/V10/doc/
ethmac10g/tags/V10/doc/transmit.pdf
ethmac10g/tags/V10/rxDAchecker.v
ethmac10g/tags/V10/10gmac.ise_ISE_Backup
ethmac10g/tags/V10/rxClkgen.v
ethmac10g/tags/V10/rxNumCounter.v
ethmac10g/tags/V10/M8_1E.v
ethmac10g/tags/V10/rxStateMachine.v
ethmac10g/tags/V10/rxLinkFaultState.v
ethmac10g/tags/V10/dcm0.v
ethmac10g/web_uploads/
ethmac10g/trunk/
ethmac10g/trunk/bench/
ethmac10g/trunk/bench/TransmitTop.mpf
ethmac10g/trunk/bench/debug.do
ethmac10g/trunk/bench/debug_large.do
ethmac10g/trunk/bench/Receive_tb.v
ethmac10g/trunk/bench/TransmitTop_tb.v
ethmac10g/trunk/bench/TransmitTop_CRC_tb.v
ethmac10g/trunk/bench/management_tb.v
ethmac10g/trunk/bench/TransmitTop_pause_tb.v
ethmac10g/trunk/bench/TransmitTop_min_frame_tb.v
ethmac10g/trunk/bench/debug_pause.do
ethmac10g/trunk/rtl/
ethmac10g/trunk/rtl/verilog/
ethmac10g/trunk/rtl/verilog/rx_engine/
ethmac10g/trunk/rtl/verilog/rx_engine/rxReceiveEngine.ucf
ethmac10g/trunk/rtl/verilog/rx_engine/timescale.v
ethmac10g/trunk/rtl/verilog/rx_engine/CRC32_D8.v
ethmac10g/trunk/rtl/verilog/rx_engine/SwitchAsyncFIFO.v
ethmac10g/trunk/rtl/verilog/rx_engine/rxReceiveEngine.v
ethmac10g/trunk/rtl/verilog/rx_engine/counter.v
ethmac10g/trunk/rtl/verilog/rx_engine/xgiga_define.v
ethmac10g/trunk/rtl/verilog/rx_engine/rxCRC.v
ethmac10g/trunk/rtl/verilog/rx_engine/SwitchSyncFIFO.v
ethmac10g/trunk/rtl/verilog/rx_engine/rxRSIO.v
ethmac10g/trunk/rtl/verilog/rx_engine/rxRSLayer.v
ethmac10g/trunk/rtl/verilog/rx_engine/rxLenTypChecker.v
ethmac10g/trunk/rtl/verilog/rx_engine/rxDAchecker.v
ethmac10g/trunk/rtl/verilog/rx_engine/CRC32_D64.v
ethmac10g/trunk/rtl/verilog/rx_engine/rxClkgen.v
ethmac10g/trunk/rtl/verilog/rx_engine/rxNumCounter.v
ethmac10g/trunk/rtl/verilog/rx_engine/rxDataPath.v
ethmac10g/trunk/rtl/verilog/rx_engine/rxStatModule.v
ethmac10g/trunk/rtl/verilog/rx_engine/rxStateMachine.v
ethmac10g/trunk/rtl/verilog/rx_engine/rxLinkFaultState.v
ethmac10g/trunk/rtl/verilog/mgmt/
ethmac10g/trunk/rtl/verilog/mgmt/management_top.v
ethmac10g/trunk/rtl/verilog/mgmt/manage_registers.v
ethmac10g/trunk/rtl/verilog/mgmt/mdio.v
ethmac10g/trunk/rtl/verilog/tx_engine/
ethmac10g/trunk/rtl/verilog/tx_engine/CRC32_D8.v
ethmac10g/trunk/rtl/verilog/tx_engine/byte_counter.v
ethmac10g/trunk/rtl/verilog/tx_engine/ack_counter.v
ethmac10g/trunk/rtl/verilog/tx_engine/CRC32_D64.v
ethmac10g/trunk/rtl/verilog/tx_engine/TransmitTop.v
ethmac10g/trunk/doc/
ethmac10g/trunk/doc/transmit.pdf
ethmac10g/trunk/doc/Receive.pdf
ethmac10g/trunk/doc/managemen
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