文件名称:UART
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- 上传时间:2013-11-30
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文件大小:1.64mb
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已下载:0次
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相关连接:无下载说明:别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容来自于网络,使用问题请自行百度
实现了UART的底层协议,加入了控制器,其波特率可以根据使用进行调整;发送模块、接收模块相互独立,互不影响。-Realization of the underlying protocol UART, joined the controller baud rate can be adjusted according to use transmission module, receiver module are independent of each other.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
UART/
UART/CONTROL.v
UART/CONTROL.v.bak
UART/db/
UART/db/altsyncram_jgc1.tdf
UART/db/prev_cmp_UART.asm.qmsg
UART/db/prev_cmp_UART.db_export.qmsg
UART/db/prev_cmp_UART.drc.qmsg
UART/db/prev_cmp_UART.eda.qmsg
UART/db/prev_cmp_UART.fit.qmsg
UART/db/prev_cmp_UART.map.qmsg
UART/db/prev_cmp_UART.merge.qmsg
UART/db/prev_cmp_UART.qmsg
UART/db/prev_cmp_UART.tan.qmsg
UART/db/UART.(0).cnf.cdb
UART/db/UART.(0).cnf.hdb
UART/db/UART.(1).cnf.cdb
UART/db/UART.(1).cnf.hdb
UART/db/UART.(10).cnf.cdb
UART/db/UART.(10).cnf.hdb
UART/db/UART.(11).cnf.cdb
UART/db/UART.(11).cnf.hdb
UART/db/UART.(12).cnf.cdb
UART/db/UART.(12).cnf.hdb
UART/db/UART.(13).cnf.cdb
UART/db/UART.(13).cnf.hdb
UART/db/UART.(14).cnf.cdb
UART/db/UART.(14).cnf.hdb
UART/db/UART.(15).cnf.cdb
UART/db/UART.(15).cnf.hdb
UART/db/UART.(16).cnf.cdb
UART/db/UART.(16).cnf.hdb
UART/db/UART.(2).cnf.cdb
UART/db/UART.(2).cnf.hdb
UART/db/UART.(3).cnf.cdb
UART/db/UART.(3).cnf.hdb
UART/db/UART.(4).cnf.cdb
UART/db/UART.(4).cnf.hdb
UART/db/UART.(5).cnf.cdb
UART/db/UART.(5).cnf.hdb
UART/db/UART.(6).cnf.cdb
UART/db/UART.(6).cnf.hdb
UART/db/UART.(7).cnf.cdb
UART/db/UART.(7).cnf.hdb
UART/db/UART.(8).cnf.cdb
UART/db/UART.(8).cnf.hdb
UART/db/UART.(9).cnf.cdb
UART/db/UART.(9).cnf.hdb
UART/db/UART.ace_cmp.bpm
UART/db/UART.ace_cmp.cdb
UART/db/UART.ace_cmp.ecobp
UART/db/UART.ace_cmp.hdb
UART/db/UART.asm.qmsg
UART/db/UART.asm_labs.ddb
UART/db/UART.atom_map.rvd
UART/db/UART.cbx.xml
UART/db/UART.cmp.bpm
UART/db/UART.cmp.cdb
UART/db/UART.cmp.ecobp
UART/db/UART.cmp.hdb
UART/db/UART.cmp.kpt
UART/db/UART.cmp.logdb
UART/db/UART.cmp.rdb
UART/db/UART.cmp.tdb
UART/db/UART.cmp0.ddb
UART/db/UART.cmp2.ddb
UART/db/UART.cmp_merge.kpt
UART/db/UART.db_export.qmsg
UART/db/UART.db_info
UART/db/UART.drc.qmsg
UART/db/UART.eco.cdb
UART/db/UART.eda.qmsg
UART/db/UART.fit.qmsg
UART/db/UART.hier_info
UART/db/UART.hif
UART/db/UART.lpc.html
UART/db/UART.lpc.rdb
UART/db/UART.lpc.txt
UART/db/UART.map.bpm
UART/db/UART.map.cdb
UART/db/UART.map.ecobp
UART/db/UART.map.hdb
UART/db/UART.map.kpt
UART/db/UART.map.logdb
UART/db/UART.map.qmsg
UART/db/UART.map_bb.cdb
UART/db/UART.map_bb.hdb
UART/db/UART.map_bb.logdb
UART/db/UART.merge.qmsg
UART/db/UART.pre_map.cdb
UART/db/UART.pre_map.hdb
UART/db/UART.rpp.qmsg
UART/db/UART.rtlv.hdb
UART/db/UART.rtlv_sg.cdb
UART/db/UART.rtlv_sg_swap.cdb
UART/db/UART.sgate.rvd
UART/db/UART.sgate_sm.rvd
UART/db/UART.sgdiff.cdb
UART/db/UART.sgdiff.hdb
UART/db/UART.sld_design_entry.sci
UART/db/UART.sld_design_entry_dsc.sci
UART/db/UART.syn_hier_info
UART/db/UART.tan.qmsg
UART/db/UART.tis_db_list.ddb
UART/db/UART.tmw_info
UART/db/UART_global_asgn_op.abo
UART/detect.v
UART/detect.v.bak
UART/incremental_db/
UART/incremental_db/compiled_partitions/
UART/incremental_db/compiled_partitions/UART.root_partition.cmp.atm
UART/incremental_db/compiled_partitions/UART.root_partition.cmp.dfp
UART/incremental_db/compiled_partitions/UART.root_partition.cmp.hdbx
UART/incremental_db/compiled_partitions/UART.root_partition.cmp.kpt
UART/incremental_db/compiled_partitions/UART.root_partition.cmp.logdb
UART/incremental_db/compiled_partitions/UART.root_partition.cmp.rcf
UART/incremental_db/compiled_partitions/UART.root_partition.map.atm
UART/incremental_db/compiled_partitions/UART.root_partition.map.dpi
UART/incremental_db/compiled_partitions/UART.root_partition.map.hdbx
UART/incremental_db/compiled_partitions/UART.root_partition.map.kpt
UART/incremental_db/README
UART/ROM.v.bak
UART/RX.v
UART/RX.v.bak
UART/RX_BPS.v
UART/RX_BPS.v.bak
UART/RX_control.v
UART/RX_control.v.bak
UART/serv_req_info.txt
UART/simulation/
UART/simulation/modelsim/
UART/simulation/modelsim/modelsim.ini
UART/simulation/modelsim/msim_transcript
UART/simulation/modelsim/rom.bsf
UART/simulation/modelsim/rom.qip
UART/simulation/modelsim/rom.v
UART/simulation/modelsim/rom_bb.v
UART/simulation/modelsim/rom_inst.v
UART/simulation/modelsim/rom_wave0.jpg
UART/simulation/modelsim/rom_waveforms.html
UART/simulation/modelsim/rtl_work/
UART/simulation/modelsim/rtl_work/@c@o@n@t@r@o@l/
UART/simulation/modelsim/rtl_work/@c@o@n@t@r@o@l/verilog.psm
UART/simulation/modelsim/rtl_work/@c@o@n@t@r@o@l/_primary.dat
UART/simulation/modelsim/rtl_work/@c@o@n@t@r@o@l/_primary.dbs
UART/simulation/modelsim/rtl_work/@c@o@n@t@r@o@l/_primary.vhd
UART/simulation/modelsim/rtl_work/@r@x/
UART/simulation/modelsim/rtl_work/@r@x/verilog.psm
UART/simulation/modelsim/rtl_work/@r@x/_primary.dat
UART/simulation/modelsim/rtl_work/@r@x/_primary.dbs
UART/simulation/modelsim/rtl_work/@r@x/_primary.vhd
UART/simulation/modelsim/rtl_work/@r@x_@b@p@s/
UART/simulation/modelsim/rtl_work/@r@x_@b@p@s/verilog.psm
UART/simulation/modelsim/rtl_work/@r@x_@b@p@s/_primary.dat
UART/simulation/modelsim/rtl_work/@r@x_@b@p@s/_primary.dbs
UART/simulation/modelsim/rtl_work/@r@x_@b@p@s/_primary.vhd
UART/simulation/modelsim/rtl_work/@r@x_control/
UART/simulation/modelsim/rtl_work/@r@x_control/verilog.psm
UART/simulation/modelsim/rtl_work/@r@x_control/_primary.dat
UART/simulation/modelsim/rtl_work/@r@x_control/_primary.dbs
UART/simulation/modelsim/rtl_work/@r@x_control/_primary.vhd
UART/simulation/modelsim/rtl_work/@t@o@p/
UART/simulation
UART/CONTROL.v
UART/CONTROL.v.bak
UART/db/
UART/db/altsyncram_jgc1.tdf
UART/db/prev_cmp_UART.asm.qmsg
UART/db/prev_cmp_UART.db_export.qmsg
UART/db/prev_cmp_UART.drc.qmsg
UART/db/prev_cmp_UART.eda.qmsg
UART/db/prev_cmp_UART.fit.qmsg
UART/db/prev_cmp_UART.map.qmsg
UART/db/prev_cmp_UART.merge.qmsg
UART/db/prev_cmp_UART.qmsg
UART/db/prev_cmp_UART.tan.qmsg
UART/db/UART.(0).cnf.cdb
UART/db/UART.(0).cnf.hdb
UART/db/UART.(1).cnf.cdb
UART/db/UART.(1).cnf.hdb
UART/db/UART.(10).cnf.cdb
UART/db/UART.(10).cnf.hdb
UART/db/UART.(11).cnf.cdb
UART/db/UART.(11).cnf.hdb
UART/db/UART.(12).cnf.cdb
UART/db/UART.(12).cnf.hdb
UART/db/UART.(13).cnf.cdb
UART/db/UART.(13).cnf.hdb
UART/db/UART.(14).cnf.cdb
UART/db/UART.(14).cnf.hdb
UART/db/UART.(15).cnf.cdb
UART/db/UART.(15).cnf.hdb
UART/db/UART.(16).cnf.cdb
UART/db/UART.(16).cnf.hdb
UART/db/UART.(2).cnf.cdb
UART/db/UART.(2).cnf.hdb
UART/db/UART.(3).cnf.cdb
UART/db/UART.(3).cnf.hdb
UART/db/UART.(4).cnf.cdb
UART/db/UART.(4).cnf.hdb
UART/db/UART.(5).cnf.cdb
UART/db/UART.(5).cnf.hdb
UART/db/UART.(6).cnf.cdb
UART/db/UART.(6).cnf.hdb
UART/db/UART.(7).cnf.cdb
UART/db/UART.(7).cnf.hdb
UART/db/UART.(8).cnf.cdb
UART/db/UART.(8).cnf.hdb
UART/db/UART.(9).cnf.cdb
UART/db/UART.(9).cnf.hdb
UART/db/UART.ace_cmp.bpm
UART/db/UART.ace_cmp.cdb
UART/db/UART.ace_cmp.ecobp
UART/db/UART.ace_cmp.hdb
UART/db/UART.asm.qmsg
UART/db/UART.asm_labs.ddb
UART/db/UART.atom_map.rvd
UART/db/UART.cbx.xml
UART/db/UART.cmp.bpm
UART/db/UART.cmp.cdb
UART/db/UART.cmp.ecobp
UART/db/UART.cmp.hdb
UART/db/UART.cmp.kpt
UART/db/UART.cmp.logdb
UART/db/UART.cmp.rdb
UART/db/UART.cmp.tdb
UART/db/UART.cmp0.ddb
UART/db/UART.cmp2.ddb
UART/db/UART.cmp_merge.kpt
UART/db/UART.db_export.qmsg
UART/db/UART.db_info
UART/db/UART.drc.qmsg
UART/db/UART.eco.cdb
UART/db/UART.eda.qmsg
UART/db/UART.fit.qmsg
UART/db/UART.hier_info
UART/db/UART.hif
UART/db/UART.lpc.html
UART/db/UART.lpc.rdb
UART/db/UART.lpc.txt
UART/db/UART.map.bpm
UART/db/UART.map.cdb
UART/db/UART.map.ecobp
UART/db/UART.map.hdb
UART/db/UART.map.kpt
UART/db/UART.map.logdb
UART/db/UART.map.qmsg
UART/db/UART.map_bb.cdb
UART/db/UART.map_bb.hdb
UART/db/UART.map_bb.logdb
UART/db/UART.merge.qmsg
UART/db/UART.pre_map.cdb
UART/db/UART.pre_map.hdb
UART/db/UART.rpp.qmsg
UART/db/UART.rtlv.hdb
UART/db/UART.rtlv_sg.cdb
UART/db/UART.rtlv_sg_swap.cdb
UART/db/UART.sgate.rvd
UART/db/UART.sgate_sm.rvd
UART/db/UART.sgdiff.cdb
UART/db/UART.sgdiff.hdb
UART/db/UART.sld_design_entry.sci
UART/db/UART.sld_design_entry_dsc.sci
UART/db/UART.syn_hier_info
UART/db/UART.tan.qmsg
UART/db/UART.tis_db_list.ddb
UART/db/UART.tmw_info
UART/db/UART_global_asgn_op.abo
UART/detect.v
UART/detect.v.bak
UART/incremental_db/
UART/incremental_db/compiled_partitions/
UART/incremental_db/compiled_partitions/UART.root_partition.cmp.atm
UART/incremental_db/compiled_partitions/UART.root_partition.cmp.dfp
UART/incremental_db/compiled_partitions/UART.root_partition.cmp.hdbx
UART/incremental_db/compiled_partitions/UART.root_partition.cmp.kpt
UART/incremental_db/compiled_partitions/UART.root_partition.cmp.logdb
UART/incremental_db/compiled_partitions/UART.root_partition.cmp.rcf
UART/incremental_db/compiled_partitions/UART.root_partition.map.atm
UART/incremental_db/compiled_partitions/UART.root_partition.map.dpi
UART/incremental_db/compiled_partitions/UART.root_partition.map.hdbx
UART/incremental_db/compiled_partitions/UART.root_partition.map.kpt
UART/incremental_db/README
UART/ROM.v.bak
UART/RX.v
UART/RX.v.bak
UART/RX_BPS.v
UART/RX_BPS.v.bak
UART/RX_control.v
UART/RX_control.v.bak
UART/serv_req_info.txt
UART/simulation/
UART/simulation/modelsim/
UART/simulation/modelsim/modelsim.ini
UART/simulation/modelsim/msim_transcript
UART/simulation/modelsim/rom.bsf
UART/simulation/modelsim/rom.qip
UART/simulation/modelsim/rom.v
UART/simulation/modelsim/rom_bb.v
UART/simulation/modelsim/rom_inst.v
UART/simulation/modelsim/rom_wave0.jpg
UART/simulation/modelsim/rom_waveforms.html
UART/simulation/modelsim/rtl_work/
UART/simulation/modelsim/rtl_work/@c@o@n@t@r@o@l/
UART/simulation/modelsim/rtl_work/@c@o@n@t@r@o@l/verilog.psm
UART/simulation/modelsim/rtl_work/@c@o@n@t@r@o@l/_primary.dat
UART/simulation/modelsim/rtl_work/@c@o@n@t@r@o@l/_primary.dbs
UART/simulation/modelsim/rtl_work/@c@o@n@t@r@o@l/_primary.vhd
UART/simulation/modelsim/rtl_work/@r@x/
UART/simulation/modelsim/rtl_work/@r@x/verilog.psm
UART/simulation/modelsim/rtl_work/@r@x/_primary.dat
UART/simulation/modelsim/rtl_work/@r@x/_primary.dbs
UART/simulation/modelsim/rtl_work/@r@x/_primary.vhd
UART/simulation/modelsim/rtl_work/@r@x_@b@p@s/
UART/simulation/modelsim/rtl_work/@r@x_@b@p@s/verilog.psm
UART/simulation/modelsim/rtl_work/@r@x_@b@p@s/_primary.dat
UART/simulation/modelsim/rtl_work/@r@x_@b@p@s/_primary.dbs
UART/simulation/modelsim/rtl_work/@r@x_@b@p@s/_primary.vhd
UART/simulation/modelsim/rtl_work/@r@x_control/
UART/simulation/modelsim/rtl_work/@r@x_control/verilog.psm
UART/simulation/modelsim/rtl_work/@r@x_control/_primary.dat
UART/simulation/modelsim/rtl_work/@r@x_control/_primary.dbs
UART/simulation/modelsim/rtl_work/@r@x_control/_primary.vhd
UART/simulation/modelsim/rtl_work/@t@o@p/
UART/simulation
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