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文件名称:SPI-Master-Core-DAC-ADC-spartan

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2014-03-03
  • 文件大小：
    1.87mb
  • 已下载：
    1次
  • 提 供 者：
    o*****
  • 相关连接：
    无
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修正介绍说明

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SPI Master Core for spartan (ADC, DAC) vhdl code
(系统自动生成,下载前可以参看下载内容)

下载文件列表

SPI Master Core DAC ADC spartan/spi.doc
SPI Master Core DAC ADC spartan/spi.pdf
SPI Master Core DAC ADC spartan/tags/asyst_2/rtl/verilog/spi_clgen.v
SPI Master Core DAC ADC spartan/tags/asyst_2/rtl/verilog/spi_defines.v
SPI Master Core DAC ADC spartan/tags/asyst_2/rtl/verilog/spi_shift.v
SPI Master Core DAC ADC spartan/tags/asyst_2/rtl/verilog/spi_top.v
SPI Master Core DAC ADC spartan/tags/asyst_2/rtl/verilog/timescale.v
SPI Master Core DAC ADC spartan/tags/asyst_3/rtl/verilog/spi_clgen.v
SPI Master Core DAC ADC spartan/tags/asyst_3/rtl/verilog/spi_defines.v
SPI Master Core DAC ADC spartan/tags/asyst_3/rtl/verilog/spi_shift.v
SPI Master Core DAC ADC spartan/tags/asyst_3/rtl/verilog/spi_top.v
SPI Master Core DAC ADC spartan/tags/asyst_3/rtl/verilog/timescale.v
SPI Master Core DAC ADC spartan/tags/initial/bench/verilog/spi_slave_model.v
SPI Master Core DAC ADC spartan/tags/initial/bench/verilog/tb_spi_top.v
SPI Master Core DAC ADC spartan/tags/initial/bench/verilog/wb_master_model.v
SPI Master Core DAC ADC spartan/tags/initial/doc/src/spi.doc
SPI Master Core DAC ADC spartan/tags/initial/rtl/verilog/spi_clgen.v
SPI Master Core DAC ADC spartan/tags/initial/rtl/verilog/spi_defines.v
SPI Master Core DAC ADC spartan/tags/initial/rtl/verilog/spi_shift.v
SPI Master Core DAC ADC spartan/tags/initial/rtl/verilog/spi_top.v
SPI Master Core DAC ADC spartan/tags/initial/rtl/verilog/timescale.v
SPI Master Core DAC ADC spartan/tags/initial/sim/run/sim
SPI Master Core DAC ADC spartan/tags/initial/sim/run/tcl.scr
SPI Master Core DAC ADC spartan/tags/rel_1/bench/verilog/spi_slave_model.v
SPI Master Core DAC ADC spartan/tags/rel_1/bench/verilog/tb_spi_top.v
SPI Master Core DAC ADC spartan/tags/rel_1/bench/verilog/wb_master_model.v
SPI Master Core DAC ADC spartan/tags/rel_1/doc/spi.pdf
SPI Master Core DAC ADC spartan/tags/rel_1/doc/src/spi.doc
SPI Master Core DAC ADC spartan/tags/rel_1/rtl/verilog/spi_clgen.v
SPI Master Core DAC ADC spartan/tags/rel_1/rtl/verilog/spi_defines.v
SPI Master Core DAC ADC spartan/tags/rel_1/rtl/verilog/spi_shift.v
SPI Master Core DAC ADC spartan/tags/rel_1/rtl/verilog/spi_top.v
SPI Master Core DAC ADC spartan/tags/rel_1/rtl/verilog/timescale.v
SPI Master Core DAC ADC spartan/tags/rel_1/sim/run/sim
SPI Master Core DAC ADC spartan/tags/rel_1/sim/run/tcl.scr
SPI Master Core DAC ADC spartan/tags/rel_2/bench/verilog/spi_slave_model.v
SPI Master Core DAC ADC spartan/tags/rel_2/bench/verilog/tb_spi_top.v
SPI Master Core DAC ADC spartan/tags/rel_2/bench/verilog/wb_master_model.v
SPI Master Core DAC ADC spartan/tags/rel_2/doc/spi.pdf
SPI Master Core DAC ADC spartan/tags/rel_2/doc/src/spi.doc
SPI Master Core DAC ADC spartan/tags/rel_2/rtl/verilog/spi_clgen.v
SPI Master Core DAC ADC spartan/tags/rel_2/rtl/verilog/spi_defines.v
SPI Master Core DAC ADC spartan/tags/rel_2/rtl/verilog/spi_shift.v
SPI Master Core DAC ADC spartan/tags/rel_2/rtl/verilog/spi_top.v
SPI Master Core DAC ADC spartan/tags/rel_2/rtl/verilog/timescale.v
SPI Master Core DAC ADC spartan/tags/rel_2/sim/run/sim
SPI Master Core DAC ADC spartan/tags/rel_2/sim/run/tcl.scr
SPI Master Core DAC ADC spartan/tags/rel_3/bench/verilog/spi_slave_model.v
SPI Master Core DAC ADC spartan/tags/rel_3/bench/verilog/tb_spi_top.v
SPI Master Core DAC ADC spartan/tags/rel_3/bench/verilog/wb_master_model.v
SPI Master Core DAC ADC spartan/tags/rel_3/doc/spi.pdf
SPI Master Core DAC ADC spartan/tags/rel_3/doc/src/spi.doc
SPI Master Core DAC ADC spartan/tags/rel_3/rtl/verilog/spi_clgen.v
SPI Master Core DAC ADC spartan/tags/rel_3/rtl/verilog/spi_defines.v
SPI Master Core DAC ADC spartan/tags/rel_3/rtl/verilog/spi_shift.v
SPI Master Core DAC ADC spartan/tags/rel_3/rtl/verilog/spi_top.v
SPI Master Core DAC ADC spartan/tags/rel_3/rtl/verilog/timescale.v
SPI Master Core DAC ADC spartan/tags/rel_3/sim/run/sim
SPI Master Core DAC ADC spartan/tags/rel_3/sim/run/tcl.scr
SPI Master Core DAC ADC spartan/tags/rel_4/bench/verilog/spi_slave_model.v
SPI Master Core DAC ADC spartan/tags/rel_4/bench/verilog/tb_spi_top.v
SPI Master Core DAC ADC spartan/tags/rel_4/bench/verilog/wb_master_model.v
SPI Master Core DAC ADC spartan/tags/rel_4/doc/spi.pdf
SPI Master Core DAC ADC spartan/tags/rel_4/doc/src/spi.doc
SPI Master Core DAC ADC spartan/tags/rel_4/rtl/verilog/spi_clgen.v
SPI Master Core DAC ADC spartan/tags/rel_4/rtl/verilog/spi_defines.v
SPI Master Core DAC ADC spartan/tags/rel_4/rtl/verilog/spi_shift.v
SPI Master Core DAC ADC spartan/tags/rel_4/rtl/verilog/spi_top.v
SPI Master Core DAC ADC spartan/tags/rel_4/rtl/verilog/timescale.v
SPI Master Core DAC ADC spartan/tags/rel_4/sim/run/sim
SPI Master Core DAC ADC spartan/tags/rel_4/sim/run/tcl.scr
SPI Master Core DAC ADC spartan/tags/rel_5/bench/verilog/spi_slave_model.v
SPI Master Core DAC ADC spartan/tags/rel_5/bench/verilog/tb_spi_top.v
SPI Master Core DAC ADC spartan/tags/rel_5/bench/verilog/wb_master_model.v
SPI Master Core DAC ADC spartan/tags/rel_5/doc/spi.pdf
SPI Master Core DAC ADC spartan/tags/rel_5/doc/src/spi.doc
SPI Master Core DAC ADC spartan/tags/rel_5/rtl/verilog/spi_clgen.v
SPI Master Core DAC ADC spartan/tags/rel_5/rtl/verilog/spi_defines.

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