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文件名称:chuzhuche

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [Text]
  • 上传时间：
    2014-03-18
  • 文件大小：
    1.27mb
  • 已下载：
    0次
  • 提 供 者：
    c***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

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基于开发板制成的出租车计费器，适用于大学生的课程设计-Based development board made of taxi meter for college curriculum design
(系统自动生成,下载前可以参看下载内容)

下载文件列表

chuzhuche/FPGA_PROJECT1.PRJFPG
chuzhuche/FPGA_Project1.PrjFpgStructure
chuzhuche/FPGA_Project1.SO
chuzhuche/History/History.event
chuzhuche/LELEchongzuo.event
chuzhuche/ProjectOutputs/$$code$$.vhd
chuzhuche/ProjectOutputs/$$temp0.vhd
chuzhuche/ProjectOutputs/Default - All Constraints/AND2S.EDN
chuzhuche/ProjectOutputs/Default - All Constraints/CDIV256DC50.EDN
chuzhuche/ProjectOutputs/Default - All Constraints/Default - All Constraints.event
chuzhuche/ProjectOutputs/Default - All Constraints/FPGA_PROJECT1.bfl
chuzhuche/ProjectOutputs/Default - All Constraints/fpga_project1.bgn
chuzhuche/ProjectOutputs/Default - All Constraints/fpga_project1.bit
chuzhuche/ProjectOutputs/Default - All Constraints/fpga_project1.bld
chuzhuche/ProjectOutputs/Default - All Constraints/FPGA_PROJECT1.edf
chuzhuche/ProjectOutputs/Default - All Constraints/FPGA_PROJECT1.FlwCmp
chuzhuche/ProjectOutputs/Default - All Constraints/FPGA_PROJECT1.mof
chuzhuche/ProjectOutputs/Default - All Constraints/FPGA_PROJECT1.mpf
chuzhuche/ProjectOutputs/Default - All Constraints/fpga_project1.ncd
chuzhuche/ProjectOutputs/Default - All Constraints/fpga_project1.ngd
chuzhuche/ProjectOutputs/Default - All Constraints/FPGA_PROJECT1.npl
chuzhuche/ProjectOutputs/Default - All Constraints/fpga_project1.pad
chuzhuche/ProjectOutputs/Default - All Constraints/fpga_project1.par
chuzhuche/ProjectOutputs/Default - All Constraints/fpga_project1.rbt
chuzhuche/ProjectOutputs/Default - All Constraints/fpga_project1.twr
chuzhuche/ProjectOutputs/Default - All Constraints/FPGA_PROJECT1.ucf
chuzhuche/ProjectOutputs/Default - All Constraints/fpga_project1.xpi
chuzhuche/ProjectOutputs/Default - All Constraints/FPGA_PROJECT1_BUILD.UCF
chuzhuche/ProjectOutputs/Default - All Constraints/fpga_project1_cclk.bgn
chuzhuche/ProjectOutputs/Default - All Constraints/fpga_project1_cclk.bit
chuzhuche/ProjectOutputs/Default - All Constraints/fpga_project1_cclk.rbt
chuzhuche/ProjectOutputs/Default - All Constraints/FPGA_PROJECT1_CoreGen.txt
chuzhuche/ProjectOutputs/Default - All Constraints/fpga_project1_map.mrp
chuzhuche/ProjectOutputs/Default - All Constraints/fpga_project1_map.ncd
chuzhuche/ProjectOutputs/Default - All Constraints/fpga_project1_map.ngm
chuzhuche/ProjectOutputs/Default - All Constraints/fpga_project1_map.pcf
chuzhuche/ProjectOutputs/Default - All Constraints/fpga_project1_pad.csv
chuzhuche/ProjectOutputs/Default - All Constraints/fpga_project1_pad.txt
chuzhuche/ProjectOutputs/Default - All Constraints/FPGA_PROJECT1_Synth.log
chuzhuche/ProjectOutputs/Default - All Constraints/IOBUF8B.VHD
chuzhuche/ProjectOutputs/Default - All Constraints/J16B_8B2.VHD
chuzhuche/ProjectOutputs/Default - All Constraints/J8B_8S.VHD
chuzhuche/ProjectOutputs/Default - All Constraints/LCD16X2A.EDN
chuzhuche/ProjectOutputs/Default - All Constraints/Sheet1.VHD
chuzhuche/ProjectOutputs/Default - All Constraints/Status Report.Txt
chuzhuche/ProjectOutputs/Default - All Constraints/_blf/FPGA_PROJECT1_body.blf
chuzhuche/ProjectOutputs/Default - All Constraints/_blf/FPGA_PROJECT1_header.blf
chuzhuche/ProjectOutputs/Default - All Constraints/_blf/IOBUF8B_body.blf
chuzhuche/ProjectOutputs/Default - All Constraints/_blf/IOBUF8B_header.blf
chuzhuche/ProjectOutputs/Default - All Constraints/_blf/JFQLCD_body.blf
chuzhuche/ProjectOutputs/Default - All Constraints/_blf/JFQLCD_header.blf
chuzhuche/ProjectOutputs/Default - All Constraints/_blf/JFQZMK_body.blf
chuzhuche/ProjectOutputs/Default - All Constraints/_blf/JFQZMK_header.blf
chuzhuche/ProjectOutputs/Default - All Constraints/_blf/LessThan_32u_32u_body.blf
chuzhuche/ProjectOutputs/Default - All Constraints/_blf/LessThan_32u_32u_header.blf
chuzhuche/ProjectOutputs/Default - All Constraints/_blf/_blf.event
chuzhuche/ProjectOutputs/Default - All Constraints/_ngo/AND2S.ngo
chuzhuche/ProjectOutputs/Default - All Constraints/_ngo/CDIV256DC50.ngo
chuzhuche/ProjectOutputs/Default - All Constraints/_ngo/fpga_project1.ngo
chuzhuche/ProjectOutputs/Default - All Constraints/_ngo/LCD16X2A.ngo
chuzhuche/ProjectOutputs/Default - All Constraints/_ngo/netlist.lst
chuzhuche/ProjectOutputs/Default - All Constraints/_ngo/_ngo.event
chuzhuche/ProjectOutputs/FPGA_PROJECT1.AL
chuzhuche/ProjectOutputs/ProjectOutputs.event
chuzhuche/ProjectOutputs/Sheet1.VHD
chuzhuche/ProjectOutputs/VHDL2.AN
chuzhuche/Sheet1 SCH ECO 2010-11-4 10-39-43.LOG
chuzhuche/Sheet1 SCH ECO 2010-11-4 10-43-45.LOG
chuzhuche/Sheet1 SCH ECO 2010-11-4 10-53-20.LOG
chuzhuche/Sheet1 SCH ECO 2010-11-4 12-04-03.LOG
chuzhuche/Sheet1 SCH ECO 2010-11-4 12-07-29.LOG
chuzhuche/Sheet1 SCH ECO 2010-11-4 12-09-50.LOG
chuzhuche/Sheet1 SCH ECO 2010-11-4 12-27-21.LOG
chuzhuche/Sheet1 SCH ECO 2010-11-4 15-23-59.LOG
chuzhuche/Sheet1 SCH ECO 2010-11-4 15-35-26.LOG
chuzhuche/Sheet1.SchDoc
chuzhuche/Sheet1.SchDocPreview
chuzhuche/Test_jfqzmk.VHDTST
chuzhuche/Test_jfqzmk.VHDTSTPreview
chuzhuche/VHDL1.Vhd
chuzhuche/VHDL1.VhdPreview
chuzhuche/VHDL2.Vhd
chuzhuche/VHDL2.VhdPreview
chuzhuche/ProjectOutputs/Default - All Constraints/_blf
chuzhuche/ProjectOutputs/Default - All Constraints/_ngo
chuzhuche/ProjectOutputs/Default - All Constraints
chuzhuche/Hi

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