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文件名称:altera_ddr_verilog

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2014-06-05
  • 文件大小：
    736.2kb
  • 已下载：
    0次
  • 提 供 者：
    刘****
  • 相关连接：
    无
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altera的DDR控制器源码（包括仿真与说明文档），DDR为mt46v4m16，Verilog-The DDR controller source of altera　(including simulation and documentation), DDR is mt46v4m16, Verilog
(系统自动生成,下载前可以参看下载内容)

下载文件列表

altera_ddr_verilog/doc/ddr_sdram.pdf
altera_ddr_verilog/model/mt46v4m16.v
altera_ddr_verilog/readme.txt
altera_ddr_verilog/route/ddr_sdram.csf
altera_ddr_verilog/route/ddr_sdram.esf
altera_ddr_verilog/route/ddr_sdram.psf
altera_ddr_verilog/route/ddr_sdram.quartus
altera_ddr_verilog/route/ddr_sdram.vqm
altera_ddr_verilog/route/pll1.v
altera_ddr_verilog/simulation/ddr_compile_all.v
altera_ddr_verilog/simulation/ddr_sdram_tb.v
altera_ddr_verilog/simulation/modelsim.ini
altera_ddr_verilog/simulation/readme.txt
altera_ddr_verilog/simulation/work/altclklock/verilog.psm
altera_ddr_verilog/simulation/work/altclklock/_primary.dat
altera_ddr_verilog/simulation/work/altclklock/_primary.vhd
altera_ddr_verilog/simulation/work/ddr_command/verilog.psm
altera_ddr_verilog/simulation/work/ddr_command/_primary.dat
altera_ddr_verilog/simulation/work/ddr_command/_primary.vhd
altera_ddr_verilog/simulation/work/ddr_control_interface/verilog.psm
altera_ddr_verilog/simulation/work/ddr_control_interface/_primary.dat
altera_ddr_verilog/simulation/work/ddr_control_interface/_primary.vhd
altera_ddr_verilog/simulation/work/ddr_data_path/verilog.psm
altera_ddr_verilog/simulation/work/ddr_data_path/_primary.dat
altera_ddr_verilog/simulation/work/ddr_data_path/_primary.vhd
altera_ddr_verilog/simulation/work/ddr_sdram/verilog.psm
altera_ddr_verilog/simulation/work/ddr_sdram/_primary.dat
altera_ddr_verilog/simulation/work/ddr_sdram/_primary.vhd
altera_ddr_verilog/simulation/work/ddr_sdram_tb/verilog.psm
altera_ddr_verilog/simulation/work/ddr_sdram_tb/_primary.dat
altera_ddr_verilog/simulation/work/ddr_sdram_tb/_primary.vhd
altera_ddr_verilog/simulation/work/mt46v4m16/verilog.psm
altera_ddr_verilog/simulation/work/mt46v4m16/_primary.dat
altera_ddr_verilog/simulation/work/mt46v4m16/_primary.vhd
altera_ddr_verilog/simulation/work/pll1/verilog.psm
altera_ddr_verilog/simulation/work/pll1/_primary.dat
altera_ddr_verilog/simulation/work/pll1/_primary.vhd
altera_ddr_verilog/simulation/work/_info
altera_ddr_verilog/source/altclklock.v
altera_ddr_verilog/source/ddr_Command.v
altera_ddr_verilog/source/ddr_control_interface.v
altera_ddr_verilog/source/ddr_data_path.v
altera_ddr_verilog/source/ddr_sdram.v
altera_ddr_verilog/source/Params.v
altera_ddr_verilog/source/pll1.v
altera_ddr_verilog/synthesis/synplicity/ddr_data_path.srm
altera_ddr_verilog/synthesis/synplicity/ddr_data_path.srr
altera_ddr_verilog/synthesis/synplicity/ddr_data_path.srs
altera_ddr_verilog/synthesis/synplicity/ddr_data_path.tlg
altera_ddr_verilog/synthesis/synplicity/ddr_data_path.xrf
altera_ddr_verilog/synthesis/synplicity/ddr_sdram.prj
altera_ddr_verilog/synthesis/synplicity/ddr_sdram.sdc
altera_ddr_verilog/synthesis/synplicity/ddr_sdram.srm
altera_ddr_verilog/synthesis/synplicity/ddr_sdram.srr
altera_ddr_verilog/synthesis/synplicity/ddr_sdram.srs
altera_ddr_verilog/synthesis/synplicity/ddr_sdram.tcl
altera_ddr_verilog/synthesis/synplicity/ddr_sdram.tlg
altera_ddr_verilog/synthesis/synplicity/ddr_sdram.vqm
altera_ddr_verilog/synthesis/synplicity/ddr_sdram.xrf
altera_ddr_verilog/synthesis/synplicity/ddr_sdram_cons.tcl
altera_ddr_verilog/synthesis/synplicity/ddr_sdram_rm.tcl
altera_ddr_verilog/simulation/work/altclklock
altera_ddr_verilog/simulation/work/ddr_command
altera_ddr_verilog/simulation/work/ddr_control_interface
altera_ddr_verilog/simulation/work/ddr_data_path
altera_ddr_verilog/simulation/work/ddr_sdram
altera_ddr_verilog/simulation/work/ddr_sdram_tb
altera_ddr_verilog/simulation/work/mt46v4m16
altera_ddr_verilog/simulation/work/pll1
altera_ddr_verilog/simulation/work
altera_ddr_verilog/synthesis/synplicity
altera_ddr_verilog/doc
altera_ddr_verilog/model
altera_ddr_verilog/route
altera_ddr_verilog/simulation
altera_ddr_verilog/source
altera_ddr_verilog/synthesis
altera_ddr_verilog

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