文件名称:2ASK
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- 上传时间：2014-06-11
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文件大小：57.16kb
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使用altera的FPGA实现2ASK的调制与解调，内含详细注释与完整工程-FPGA implementation using Altera modulation and demodulation of 2ASK, containing detailed notes and complete project
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下载文件列表
2ASK/
2ASK/pro/
2ASK/sim/
2ASK/sim/two_ASK.cr.mti
2ASK/sim/two_ASK.mpf
2ASK/sim/vsim.wlf
2ASK/sim/work/
2ASK/sim/work/@a@s@k_two/
2ASK/sim/work/@a@s@k_two/_primary.dat
2ASK/sim/work/@a@s@k_two/_primary.dbs
2ASK/sim/work/@a@s@k_two/_primary.vhd
2ASK/sim/work/@a@s@k_two/verilog.asm
2ASK/sim/work/@a@s@k_two/verilog.rw
2ASK/sim/work/_info
2ASK/sim/work/_temp/
2ASK/sim/work/_temp/vlog0kq5x6
2ASK/sim/work/_temp/vlog903jr7
2ASK/sim/work/_temp/vlogatj86b
2ASK/sim/work/_temp/vlogb55i87
2ASK/sim/work/_temp/vlogg7bv0e
2ASK/sim/work/_temp/vlogggbvxd
2ASK/sim/work/_temp/vlogiinv63
2ASK/sim/work/_temp/vlogivnv33
2ASK/sim/work/_temp/vlogrxdesq
2ASK/sim/work/_temp/vlogy0b0dd
2ASK/sim/work/_temp/vlogy2qk13
2ASK/sim/work/_temp/vlogybqky2
2ASK/sim/work/_vmake
2ASK/sim/work/tb_two_@a@s@k/
2ASK/sim/work/tb_two_@a@s@k/_primary.dat
2ASK/sim/work/tb_two_@a@s@k/_primary.dbs
2ASK/sim/work/tb_two_@a@s@k/_primary.vhd
2ASK/sim/work/tb_two_@a@s@k/verilog.asm
2ASK/sim/work/tb_two_@a@s@k/verilog.rw
2ASK/sim/work/two_@a@s@k/
2ASK/sim/work/two_@a@s@k/_primary.dat
2ASK/sim/work/two_@a@s@k/_primary.dbs
2ASK/sim/work/two_@a@s@k/_primary.vhd
2ASK/sim/work/two_@a@s@k/verilog.asm
2ASK/sim/work/two_@a@s@k/verilog.rw
2ASK/sim/work/two_@a@s@k_two/
2ASK/sim/work/two_@a@s@k_two/_primary.dat
2ASK/sim/work/two_@a@s@k_two/_primary.dbs
2ASK/sim/work/two_@a@s@k_two/_primary.vhd
2ASK/sim/work/two_@a@s@k_two/verilog.asm
2ASK/sim/work/two_@a@s@k_two/verilog.rw
2ASK/src/
2ASK/src/ASK_two.v
2ASK/src/ASK_two.v.bak
2ASK/src/src/
2ASK/src/src/tb_ASK.v.bak
2ASK/src/tb_ASK.v
2ASK/src/tb_two_ASK.v
2ASK/src/tb_two_ASK.v.bak
2ASK/src/two_ASK.v
2ASK/src/two_ASK.v.bak
2ASK/src/two_ASK_two.v
2ASK/src/two_ASK_two.v.bak
2ASK/pro/
2ASK/sim/
2ASK/sim/two_ASK.cr.mti
2ASK/sim/two_ASK.mpf
2ASK/sim/vsim.wlf
2ASK/sim/work/
2ASK/sim/work/@a@s@k_two/
2ASK/sim/work/@a@s@k_two/_primary.dat
2ASK/sim/work/@a@s@k_two/_primary.dbs
2ASK/sim/work/@a@s@k_two/_primary.vhd
2ASK/sim/work/@a@s@k_two/verilog.asm
2ASK/sim/work/@a@s@k_two/verilog.rw
2ASK/sim/work/_info
2ASK/sim/work/_temp/
2ASK/sim/work/_temp/vlog0kq5x6
2ASK/sim/work/_temp/vlog903jr7
2ASK/sim/work/_temp/vlogatj86b
2ASK/sim/work/_temp/vlogb55i87
2ASK/sim/work/_temp/vlogg7bv0e
2ASK/sim/work/_temp/vlogggbvxd
2ASK/sim/work/_temp/vlogiinv63
2ASK/sim/work/_temp/vlogivnv33
2ASK/sim/work/_temp/vlogrxdesq
2ASK/sim/work/_temp/vlogy0b0dd
2ASK/sim/work/_temp/vlogy2qk13
2ASK/sim/work/_temp/vlogybqky2
2ASK/sim/work/_vmake
2ASK/sim/work/tb_two_@a@s@k/
2ASK/sim/work/tb_two_@a@s@k/_primary.dat
2ASK/sim/work/tb_two_@a@s@k/_primary.dbs
2ASK/sim/work/tb_two_@a@s@k/_primary.vhd
2ASK/sim/work/tb_two_@a@s@k/verilog.asm
2ASK/sim/work/tb_two_@a@s@k/verilog.rw
2ASK/sim/work/two_@a@s@k/
2ASK/sim/work/two_@a@s@k/_primary.dat
2ASK/sim/work/two_@a@s@k/_primary.dbs
2ASK/sim/work/two_@a@s@k/_primary.vhd
2ASK/sim/work/two_@a@s@k/verilog.asm
2ASK/sim/work/two_@a@s@k/verilog.rw
2ASK/sim/work/two_@a@s@k_two/
2ASK/sim/work/two_@a@s@k_two/_primary.dat
2ASK/sim/work/two_@a@s@k_two/_primary.dbs
2ASK/sim/work/two_@a@s@k_two/_primary.vhd
2ASK/sim/work/two_@a@s@k_two/verilog.asm
2ASK/sim/work/two_@a@s@k_two/verilog.rw
2ASK/src/
2ASK/src/ASK_two.v
2ASK/src/ASK_two.v.bak
2ASK/src/src/
2ASK/src/src/tb_ASK.v.bak
2ASK/src/tb_ASK.v
2ASK/src/tb_two_ASK.v
2ASK/src/tb_two_ASK.v.bak
2ASK/src/two_ASK.v
2ASK/src/two_ASK.v.bak
2ASK/src/two_ASK_two.v
2ASK/src/two_ASK_two.v.bak
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