文件名称:pipeline10
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- 上传时间：2014-07-04
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文件大小：24.29kb
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用verilog实现嵌入式系统的处理器的五级流水线。-realizing the five stages of cpu in the embedded system with the verilog language
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下载文件列表
pipeline10/EX.v
pipeline10/EX_Alu.v
pipeline10/EX_Branch.v
pipeline10/EX_Forward.v
pipeline10/EX_MEM.v
pipeline10/EX_Membranch.v
pipeline10/EX_Memread.v
pipeline10/EX_Memwrite.v
pipeline10/EX_Mux_rd.v
pipeline10/EX_Mux_rt.v
pipeline10/EX_Regwrite.v
pipeline10/EX_Shift.v
pipeline10/GLOBAL.v
pipeline10/ID.v
pipeline10/ID_Branch.v
pipeline10/ID_Control.v
pipeline10/ID_Data.v
pipeline10/ID_EX.v
pipeline10/ID_Hazard.v
pipeline10/ID_ReadWrite.v
pipeline10/IF.v
pipeline10/IF_PC.v
pipeline10/IF_REG.v
pipeline10/MEM.v
pipeline10/MEM_Branch.v
pipeline10/MEM_EX_Error.v
pipeline10/MEM_ReadWrite.v
pipeline10/MEM_WB.v
pipeline10/testbench.v
pipeline10/TOP.v
pipeline10/WB.v
pipeline10
pipeline10/EX_Alu.v
pipeline10/EX_Branch.v
pipeline10/EX_Forward.v
pipeline10/EX_MEM.v
pipeline10/EX_Membranch.v
pipeline10/EX_Memread.v
pipeline10/EX_Memwrite.v
pipeline10/EX_Mux_rd.v
pipeline10/EX_Mux_rt.v
pipeline10/EX_Regwrite.v
pipeline10/EX_Shift.v
pipeline10/GLOBAL.v
pipeline10/ID.v
pipeline10/ID_Branch.v
pipeline10/ID_Control.v
pipeline10/ID_Data.v
pipeline10/ID_EX.v
pipeline10/ID_Hazard.v
pipeline10/ID_ReadWrite.v
pipeline10/IF.v
pipeline10/IF_PC.v
pipeline10/IF_REG.v
pipeline10/MEM.v
pipeline10/MEM_Branch.v
pipeline10/MEM_EX_Error.v
pipeline10/MEM_ReadWrite.v
pipeline10/MEM_WB.v
pipeline10/testbench.v
pipeline10/TOP.v
pipeline10/WB.v
pipeline10
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