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文件名称:DDR2_VERILOG

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [HTML]
  • 上传时间：
    2014-07-11
  • 文件大小：
    1.73mb
  • 已下载：
    0次
  • 提 供 者：
    王***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

基于FPGA的DDR2_SDRAM的实现Verilog代码，比较实用，经过仿真验证。-Based on the FPGA implementation of DDR2_SDRAM Verilog code, more practical, proven by simulation.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

DDR2_VERILOG/trunk/Buttons_VHDL.vhd
DDR2_VERILOG/trunk/Clock_VHDL.vhd
DDR2_VERILOG/trunk/DDR2_Control_VHDL.vhd
DDR2_VERILOG/trunk/DDR2_liesmich.txt
DDR2_VERILOG/trunk/DDR2_readme.txt
DDR2_VERILOG/trunk/DDR2_Read_VHDL.vhd
DDR2_VERILOG/trunk/DDR2_Write_VHDL.vhd
DDR2_VERILOG/trunk/impact.xsl
DDR2_VERILOG/trunk/impact_impact.xwbt
DDR2_VERILOG/trunk/ipcore_dir/DDR2_Ram_Core/user_design/par/UB_DDR2_64bit_UCF.ucf
DDR2_VERILOG/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core.vhd
DDR2_VERILOG/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_cal_ctl.vhd
DDR2_VERILOG/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_cal_top.vhd
DDR2_VERILOG/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_clk_dcm.vhd
DDR2_VERILOG/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_controller_0.vhd
DDR2_VERILOG/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_controller_iobs_0.vhd
DDR2_VERILOG/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_data_path_0.vhd
DDR2_VERILOG/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_data_path_iobs_0.vhd
DDR2_VERILOG/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_data_read_0.vhd
DDR2_VERILOG/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_data_read_controller_0.vhd
DDR2_VERILOG/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_data_write_0.vhd
DDR2_VERILOG/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_dqs_delay_0.vhd
DDR2_VERILOG/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_fifo_0_wr_en_0.vhd
DDR2_VERILOG/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_fifo_1_wr_en_0.vhd
DDR2_VERILOG/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_infrastructure.vhd
DDR2_VERILOG/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_infrastructure_iobs_0.vhd
DDR2_VERILOG/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_infrastructure_top.vhd
DDR2_VERILOG/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_iobs_0.vhd
DDR2_VERILOG/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_parameters_0.vhd
DDR2_VERILOG/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_ram8d_0.vhd
DDR2_VERILOG/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_rd_gray_cntr.vhd
DDR2_VERILOG/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_s3_dm_iob.vhd
DDR2_VERILOG/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_s3_dqs_iob.vhd
DDR2_VERILOG/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_s3_dq_iob.vhd
DDR2_VERILOG/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_tap_dly.vhd
DDR2_VERILOG/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_top_0.vhd
DDR2_VERILOG/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_wr_gray_cntr.vhd
DDR2_VERILOG/trunk/iseconfig/Prj_12_DDR2.projectmgr
DDR2_VERILOG/trunk/iseconfig/Top_Modul_VHDL.xreport
DDR2_VERILOG/trunk/MIG_Settings/b01_part.JPG
DDR2_VERILOG/trunk/MIG_Settings/b02_generation.JPG
DDR2_VERILOG/trunk/MIG_Settings/b03_advanced.JPG
DDR2_VERILOG/trunk/MIG_Settings/b04_mig_361.JPG
DDR2_VERILOG/trunk/MIG_Settings/m01_customize.JPG
DDR2_VERILOG/trunk/MIG_Settings/m02_Create_Design.JPG
DDR2_VERILOG/trunk/MIG_Settings/m03_FPGAs.JPG
DDR2_VERILOG/trunk/MIG_Settings/m04_Memory.JPG
DDR2_VERILOG/trunk/MIG_Settings/m05_Controller.JPG
DDR2_VERILOG/trunk/MIG_Settings/m06_Options.JPG
DDR2_VERILOG/trunk/MIG_Settings/m07_Options2.JPG
DDR2_VERILOG/trunk/MIG_Settings/m08_Pins.JPG
DDR2_VERILOG/trunk/MIG_Settings/m09_Bank.JPG
DDR2_VERILOG/trunk/MIG_Settings/m10_Summary.JPG
DDR2_VERILOG/trunk/MIG_Settings/m11_License.JPG
DDR2_VERILOG/trunk/MIG_Settings/m12_PCB.JPG
DDR2_VERILOG/trunk/MIG_Settings/m13_Design.JPG
DDR2_VERILOG/trunk/MIG_Settings/m14_Coregen_Readme.JPG
DDR2_VERILOG/trunk/Prj12_Impact.ipf
DDR2_VERILOG/trunk/Prj_12_DDR2.gise
DDR2_VERILOG/trunk/Prj_12_DDR2.xise
DDR2_VERILOG/trunk/Top_Modul_VHDL.vhd
DDR2_VERILOG/trunk/Top_Modul_VHDL_bitgen.xwbt
DDR2_VERILOG/trunk/Top_Modul_VHDL_guide.ncd
DDR2_VERILOG/trunk/Top_Modul_VHDL_summary.html
DDR2_VERILOG/trunk/UB_Clock_UCF.ucf
DDR2_VERILOG/trunk/UB_Led_BUS_UCF.ucf
DDR2_VERILOG/trunk/UB_Schalter_BUS_UCF.ucf
DDR2_VERILOG/trunk/UB_Taster_BUS_UCF.ucf
DDR2_VERILOG/trunk/UB_Y-Led_UCF.ucf
DDR2_VERILOG/trunk/webtalk.log
DDR2_VERILOG/trunk/webtalk_impact.xml
DDR2_VERILOG/trunk/ipcore_dir/DDR2_Ram_Core/user_design/par
DDR2_VERILOG/trunk/ipcore_dir/DDR2_Ram_Core/user_design/rtl
DDR2_VERILOG/trunk/ipcore_dir/DDR2_Ram_Core/user_design
DDR2_VERILOG/trunk/ipcore_dir/DDR2_Ram_Core
DDR2_VERILOG/trunk/Prj12_Impact_xdb/tmp
DDR2_VERILOG/trunk/ipcore_dir
DDR2_VERILOG/trunk/iseconfig
DDR2_VERILOG/trunk/MIG_Settings
DDR2_VERILOG/trunk/Prj12_Impact_xdb
DDR2_VERILOG/trunk/_xmsgs
DDR2_VERILOG/branches
DDR2_VERILOG/tags
DDR2_VERILOG/trunk
DDR2_VERILOG

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