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文件名称:Verilog

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [WORD]
  • 上传时间：
    2014-08-09
  • 文件大小：
    1.85mb
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    0次
  • 提 供 者：
    英***
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    无
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书本Verilog设计与验证的书本源码，望能帮助到有需要的人！-Books books Verilog design and verification code, hope to help the people in need!
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Verilog设计与验证/Example-4-17/asyn_rst/asyn_rst.prd
Verilog设计与验证/Example-4-17/asyn_rst/asyn_rst.prj
Verilog设计与验证/Example-4-17/asyn_rst/asyn_rst.v
Verilog设计与验证/Example-4-17/asyn_rst/rev_1/asyn_rst.edn
Verilog设计与验证/Example-4-17/asyn_rst/rev_1/asyn_rst.fse
Verilog设计与验证/Example-4-17/asyn_rst/rev_1/asyn_rst.prf
Verilog设计与验证/Example-4-17/asyn_rst/rev_1/asyn_rst.srm
Verilog设计与验证/Example-4-17/asyn_rst/rev_1/asyn_rst.srr
Verilog设计与验证/Example-4-17/asyn_rst/rev_1/asyn_rst.srs
Verilog设计与验证/Example-4-17/asyn_rst/rev_1/asyn_rst.tlg
Verilog设计与验证/Example-4-17/asyn_rst/rev_1/AutoConstraint_asyn_rst.sdc
Verilog设计与验证/Example-4-17/asyn_rst/rev_1/generic.fse
Verilog设计与验证/Example-4-17/asyn_rst/rev_1/generic.srd
Verilog设计与验证/Example-4-17/asyn_rst/rev_1/syntmp/asyn_rst.msg
Verilog设计与验证/Example-4-17/asyn_rst/rev_1/syntmp/asyn_rst.plg
Verilog设计与验证/Example-4-17/asyn_rst_syn_release/asyn_rst_syn_release.v
Verilog设计与验证/Example-4-17/syn_rst/rev_2/AutoConstraint_syn_rst.sdc
Verilog设计与验证/Example-4-17/syn_rst/rev_2/generic.fse
Verilog设计与验证/Example-4-17/syn_rst/rev_2/generic.srd
Verilog设计与验证/Example-4-17/syn_rst/rev_2/syntmp/syn_rst.msg
Verilog设计与验证/Example-4-17/syn_rst/rev_2/syntmp/syn_rst.plg
Verilog设计与验证/Example-4-17/syn_rst/rev_2/syn_rst.edn
Verilog设计与验证/Example-4-17/syn_rst/rev_2/syn_rst.fse
Verilog设计与验证/Example-4-17/syn_rst/rev_2/syn_rst.prf
Verilog设计与验证/Example-4-17/syn_rst/rev_2/syn_rst.srm
Verilog设计与验证/Example-4-17/syn_rst/rev_2/syn_rst.srr
Verilog设计与验证/Example-4-17/syn_rst/rev_2/syn_rst.srs
Verilog设计与验证/Example-4-17/syn_rst/rev_2/syn_rst.tlg
Verilog设计与验证/Example-4-17/syn_rst/syntmp.msg
Verilog设计与验证/Example-4-17/syn_rst/syn_rst.prd
Verilog设计与验证/Example-4-17/syn_rst/syn_rst.prj
Verilog设计与验证/Example-4-17/syn_rst/syn_rst.v
Verilog设计与验证/Example-4-17/示例说明.doc
Verilog设计与验证/Example-4-20/case/case1.v
Verilog设计与验证/Example-4-20/case/PrecisionRTL/case.psp
Verilog设计与验证/Example-4-20/case/PrecisionRTL/case_impl_1/case1.edf
Verilog设计与验证/Example-4-20/case/PrecisionRTL/case_impl_1/case1.prf
Verilog设计与验证/Example-4-20/case/PrecisionRTL/case_impl_1/case1.xdb
Verilog设计与验证/Example-4-20/case/PrecisionRTL/case_impl_1/case1_area.rep
Verilog设计与验证/Example-4-20/case/PrecisionRTL/case_impl_1/case1_con_rep.sdc
Verilog设计与验证/Example-4-20/case/PrecisionRTL/case_impl_1/case1_rtl.ixdb
Verilog设计与验证/Example-4-20/case/PrecisionRTL/case_impl_1/case1_tech_con_rep.sdc
Verilog设计与验证/Example-4-20/case/PrecisionRTL/case_impl_1/case1_timing.rep
Verilog设计与验证/Example-4-20/case/PrecisionRTL/case_impl_1/case_impl_1.psi
Verilog设计与验证/Example-4-20/case/PrecisionRTL/case_impl_1/hdlAnalyze_verilogfile
Verilog设计与验证/Example-4-20/case/PrecisionRTL/case_impl_1/precision.log
Verilog设计与验证/Example-4-20/case/PrecisionRTL/case_impl_1/precision_rtl.sdc
Verilog设计与验证/Example-4-20/case/PrecisionRTL/case_impl_1/precision_tech.sdc
Verilog设计与验证/Example-4-20/case/PrecisionRTL/case_impl_1/rtlc.out/.rtlc_compile
Verilog设计与验证/Example-4-20/case/PrecisionRTL/case_impl_1/rtlc.out/.top
Verilog设计与验证/Example-4-20/case/PrecisionRTL/case_impl_1/rtlc.out/autotop.conf
Verilog设计与验证/Example-4-20/case/PrecisionRTL/case_impl_1/rtlc.out/depend/TOPMODULE.list
Verilog设计与验证/Example-4-20/case/PrecisionRTL/case_impl_1/rtlc.out/INCR/emptymod.list
Verilog设计与验证/Example-4-20/case/PrecisionRTL/case_impl_1/rtlc.out/INCR/hier.list
Verilog设计与验证/Example-4-20/case/PrecisionRTL/case_impl_1/rtlc.out/INCR/incr_driver.log
Verilog设计与验证/Example-4-20/case/PrecisionRTL/case_impl_1/rtlc.out/INCR/incr_rtlc.log
Verilog设计与验证/Example-4-20/case/PrecisionRTL/case_impl_1/rtlc.out/legalmodmap.db
Verilog设计与验证/Example-4-20/case/PrecisionRTL/case_impl_1/rtlc.out/rtlc.args
Verilog设计与验证/Example-4-20/case/PrecisionRTL/case_impl_1/rtlc.out/rtlc_args1.file
Verilog设计与验证/Example-4-20/case/PrecisionRTL/case_impl_1/rtlc.out/vmw.mem_contents
Verilog设计与验证/Example-4-20/case/PrecisionRTL/case_impl_1/rtlc_libs/work/case1.mod
Verilog设计与验证/Example-4-20/case/PrecisionRTL/case_impl_1/rtlc_libs/work/case1.mod.body
Verilog设计与验证/Example-4-20/case/PrecisionRTL/case_impl_1/rtlc_libs/work/rtlc_version_info
Verilog设计与验证/Example-4-20/case/PrecisionRTL/case_impl_1/unfolded_operators.txt
Verilog设计与验证/Example-4-20/case/PrecisionRTL/case_RTL_schematic.bmp
Verilog设计与验证/Example-4-20/case/PrecisionRTL/case_schematic.bmp
Verilog设计与验证/Example-4-20/case/PrecisionRTL/Thumbs.db
Verilog设计与验证/Example-4-20/case/SynplifyPro/case1.prd
Verilog设计与验证/Example-4-20/case/SynplifyPro/case1.prj
Verilog设计与验证/Example-4-20/case/SynplifyPro/case_rtl_view.bmp
Verilog设计与验证/Example-4-20/case/SynplifyPro/case_tech_view.bmp
Verilog设计与验证/Example-4-20/case/SynplifyPro/rev_2/AutoConstraint_case1.sdc
Verilog设计与验证/Example-4-20/case/SynplifyPro/rev_2/case1.edn
Verilog设计与验证/Example-4-20/case/SynplifyPro/rev_2/case1.fse
Verilog设计与验证/Example-4-20/case/SynplifyPro/rev_2/case1.prf
Verilog设计与验证/Example-4-20/case/SynplifyPro/rev_2/case1.srm
Verilog设计与验证/Example-4-20/case/SynplifyPro/rev_2/case1.srr
Verilog设计与验证/Example-4-20/case/SynplifyPro/rev_2/case1.srs
Verilog设计与验证/Example-4-20/case/SynplifyPro/rev_2/case1.tlg
Verilog设计与验证/Example-4-20/case/SynplifyPro/rev_2/generic.fse
Verilog设计与验证/Example-4-20/case/SynplifyPro/rev_2/generic.srd
Verilog设计与验证/

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