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文件名称:cnt

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2014-11-03
  • 文件大小：
    2.95mb
  • 已下载：
    0次
  • 提 供 者：
    喻****
  • 相关连接：
    无
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在ise开发环境下，建立顶层模块和子模块的层次结构，其实现的功能是一个可复位课暂停开始继续的建议秒表-In ise development environment, establish a hierarchy of top-level modules and sub-modules, and its function is to achieve a resettable class resumes proposal to suspend the stopwatch
(系统自动生成,下载前可以参看下载内容)

下载文件列表

FPGA_310_B_源码/sen_cnt/.lso
FPGA_310_B_源码/sen_cnt/counter.cmd_log
FPGA_310_B_源码/sen_cnt/counter.prj
FPGA_310_B_源码/sen_cnt/counter.spl
FPGA_310_B_源码/sen_cnt/counter.stx
FPGA_310_B_源码/sen_cnt/counter.sym
FPGA_310_B_源码/sen_cnt/counter.tfi
FPGA_310_B_源码/sen_cnt/counter.v
FPGA_310_B_源码/sen_cnt/counter.xst
FPGA_310_B_源码/sen_cnt/display.cmd_log
FPGA_310_B_源码/sen_cnt/display.spl
FPGA_310_B_源码/sen_cnt/display.sym
FPGA_310_B_源码/sen_cnt/display.tfi
FPGA_310_B_源码/sen_cnt/display.v
FPGA_310_B_源码/sen_cnt/ipcore_dir/coregen.cgp
FPGA_310_B_源码/sen_cnt/ipcore_dir/coregen.log
FPGA_310_B_源码/sen_cnt/ipcore_dir/create_ram.tcl
FPGA_310_B_源码/sen_cnt/ipcore_dir/edit_ram.tcl
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/blk_mem_gen_v7_3_readme.txt
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/doc/blk_mem_gen_v7_3_vinfo.html
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/doc/pg058-blk-mem-gen.pdf
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/example_design/ram_exdes.ucf
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/example_design/ram_exdes.vhd
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/example_design/ram_exdes.xdc
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/example_design/ram_prod.vhd
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/implement/implement.bat
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/implement/implement.sh
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/implement/planAhead_ise.bat
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/implement/planAhead_ise.sh
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/implement/planAhead_ise.tcl
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/implement/xst.prj
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/implement/xst.scr
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/simulation/addr_gen.vhd
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/simulation/bmg_stim_gen.vhd
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/simulation/bmg_tb_pkg.vhd
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/simulation/checker.vhd
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/simulation/data_gen.vhd
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/simulation/functional/simcmds.tcl
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/simulation/functional/simulate_isim.bat
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/simulation/functional/simulate_mti.bat
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/simulation/functional/simulate_mti.do
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/simulation/functional/simulate_mti.sh
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/simulation/functional/simulate_ncsim.sh
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/simulation/functional/simulate_vcs.sh
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/simulation/functional/ucli_commands.key
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/simulation/functional/vcs_session.tcl
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/simulation/functional/wave_mti.do
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/simulation/functional/wave_ncsim.sv
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/simulation/ram_synth.vhd
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/simulation/ram_tb.vhd
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/simulation/random.vhd
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/simulation/timing/simcmds.tcl
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/simulation/timing/simulate_isim.bat
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/simulation/timing/simulate_mti.bat
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/simulation/timing/simulate_mti.do
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/simulation/timing/simulate_mti.sh
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/simulation/timing/simulate_ncsim.sh
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/simulation/timing/simulate_vcs.sh
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/simulation/timing/ucli_commands.key
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/simulation/timing/vcs_session.tcl
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/simulation/timing/wave_mti.do
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram/simulation/timing/wave_ncsim.sv
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram.asy
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram.gise
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram.ncf
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram.ngc
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram.sym
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram.v
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram.veo
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram.xco
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram.xise
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram_flist.txt
FPGA_310_B_源码/sen_cnt/ipcore_dir/ram_xmdf.tcl
FPGA_310_B_源码/sen_cnt/ipcore_dir/summary.log
FPGA_310_B_源码/sen_cnt/ipcore_dir/tmp/ram.lso
FPGA_310_B_源码/sen_cnt/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs
FPGA_310_B_源码/sen_cnt/ipcore_dir/tmp/_xmsgs/xst.xmsgs
FPGA_310_B_源码/sen_cnt/ipcore_dir/_xmsgs/cg.xmsgs
FPGA_310_B_源码/sen_cnt/ipcore_dir/_xmsgs/pn_parser.xmsgs
FPGA_310_B_源码/sen_cnt/iseconfig/sen_cnt.projectmgr
FPGA_310_B_源码/sen_cnt/iseconfig/top.xreport
FPGA_310_B_源码/sen_cnt/process.cmd_log
FPGA_310_B_源码/sen_cnt/process.spl
FPGA_310_B_源码/sen_cnt/process.sym
FPGA_310_B_源码/sen_cnt/process.tfi
FPGA_310_B_源码/sen_cnt/process.v
FPGA_310_B_源码/sen_cnt/ram_w_r.cmd_log
FPGA_310_B_源码/sen_cnt/ram_w_r.spl
FPGA_310_B_源码/sen_cnt/ram_w_r.sym
FPGA_310_B_源码/sen_cnt/ram_w_r.tfi
FPGA_310_B_源码/sen_cnt/ram_w_r.v
FPGA_310_B_源码/sen_cnt/sen_cnt.gise
FPGA_310_B_源码/sen_cnt/sen_cnt.xise
FPGA_310_B_源码/sen_cnt/top.bgn
FPGA_310_B_源码/sen_cnt/top.bit
FPGA_310_B_源码/sen_cnt/top.bld
FPGA_310_B_源码/sen_cnt/top.cmd_log
FPGA_310_B_源码/sen_cnt/top.drc
FPGA_310_B_源码/sen_cnt/top.lso
FPGA_310_B_源码/sen_cnt/to

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