文件名称:DE2_TV
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- 上传时间：2014-11-10
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文件大小：209.54kb
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本代码为Altera DE2开发板例程源码，（FPGA：EP2C35F672C6）quartus II 9.0以上可以编译（随板源码为7.2以下版本，在9.0以上版本编译会报错）。本代码实现一个音视频播放器TV_BOX。-This demonstration plays video and audio input a DVD player using the VGA output and audio CODEC on the DE2 board. There are two major blocks in the circuit, called I2C_AV_Config and TV_to_VGA. The TV_to_VGA block consists
of the ITU-R 656 Decoder, SDRAM Frame Buffer, YUV422 to YUV444, YCrCb to RGB, and VGA Controller.
of the ITU-R 656 Decoder, SDRAM Frame Buffer, YUV422 to YUV444, YCrCb to RGB, and VGA Controller.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
DE2_TV/DE2_TV.done
DE2_TV/DE2_TV.fit.smsg
DE2_TV/DE2_TV.fit.summary
DE2_TV/DE2_TV.jdi
DE2_TV/DE2_TV.map.summary
DE2_TV/DE2_TV.pin
DE2_TV/DE2_TV.pof
DE2_TV/DE2_TV.qpf
DE2_TV/DE2_TV.qsf
DE2_TV/DE2_TV.sdc
DE2_TV/DE2_TV.sof
DE2_TV/DE2_TV.sta.summary
DE2_TV/DE2_TV.v
DE2_TV/DE2_TV_assignment_defaults.qdf
DE2_TV/demo_batch/DE2_TV.sof
DE2_TV/demo_batch/test.bat
DE2_TV/DIV.qip
DE2_TV/greybox_tmp/cbx_args.txt
DE2_TV/Line_Buffer.qip
DE2_TV/MAC_3.qip
DE2_TV/Sdram_Control_4Port/command.v
DE2_TV/Sdram_Control_4Port/control_interface.v
DE2_TV/Sdram_Control_4Port/greybox_tmp/cbx_args.txt
DE2_TV/Sdram_Control_4Port/Sdram_Control_4Port.v
DE2_TV/Sdram_Control_4Port/Sdram_Params.h
DE2_TV/Sdram_Control_4Port/Sdram_PLL.ppf
DE2_TV/Sdram_Control_4Port/Sdram_PLL.qip
DE2_TV/Sdram_Control_4Port/Sdram_PLL.v
DE2_TV/Sdram_Control_4Port/Sdram_RD_FIFO.qip
DE2_TV/Sdram_Control_4Port/Sdram_RD_FIFO.v
DE2_TV/Sdram_Control_4Port/Sdram_WR_FIFO.qip
DE2_TV/Sdram_Control_4Port/Sdram_WR_FIFO.v
DE2_TV/Sdram_Control_4Port/sdr_data_path.v
DE2_TV/Sdram_PLL.qip
DE2_TV/Sdram_WR_FIFO.qip
DE2_TV/v/AUDIO_DAC.v
DE2_TV/v/DIV.v
DE2_TV/v/I2C_AV_Config.v
DE2_TV/v/I2C_Controller.v
DE2_TV/v/ITU_656_Decoder.v
DE2_TV/v/Line_Buffer.v
DE2_TV/v/MAC_3.v
DE2_TV/v/PLL.v
DE2_TV/v/Reset_Delay.v
DE2_TV/v/SEG7_LUT.v
DE2_TV/v/SEG7_LUT_8.v
DE2_TV/v/TD_Detect.v
DE2_TV/v/TP_RAM.v
DE2_TV/v/VGA_Ctrl.v
DE2_TV/v/YCbCr2RGB.v
DE2_TV/v/YUV422_to_444.v
DE2_TV/Sdram_Control_4Port/greybox_tmp
DE2_TV/demo_batch
DE2_TV/greybox_tmp
DE2_TV/Sdram_Control_4Port
DE2_TV/v
DE2_TV
DE2_TV/DE2_TV.fit.smsg
DE2_TV/DE2_TV.fit.summary
DE2_TV/DE2_TV.jdi
DE2_TV/DE2_TV.map.summary
DE2_TV/DE2_TV.pin
DE2_TV/DE2_TV.pof
DE2_TV/DE2_TV.qpf
DE2_TV/DE2_TV.qsf
DE2_TV/DE2_TV.sdc
DE2_TV/DE2_TV.sof
DE2_TV/DE2_TV.sta.summary
DE2_TV/DE2_TV.v
DE2_TV/DE2_TV_assignment_defaults.qdf
DE2_TV/demo_batch/DE2_TV.sof
DE2_TV/demo_batch/test.bat
DE2_TV/DIV.qip
DE2_TV/greybox_tmp/cbx_args.txt
DE2_TV/Line_Buffer.qip
DE2_TV/MAC_3.qip
DE2_TV/Sdram_Control_4Port/command.v
DE2_TV/Sdram_Control_4Port/control_interface.v
DE2_TV/Sdram_Control_4Port/greybox_tmp/cbx_args.txt
DE2_TV/Sdram_Control_4Port/Sdram_Control_4Port.v
DE2_TV/Sdram_Control_4Port/Sdram_Params.h
DE2_TV/Sdram_Control_4Port/Sdram_PLL.ppf
DE2_TV/Sdram_Control_4Port/Sdram_PLL.qip
DE2_TV/Sdram_Control_4Port/Sdram_PLL.v
DE2_TV/Sdram_Control_4Port/Sdram_RD_FIFO.qip
DE2_TV/Sdram_Control_4Port/Sdram_RD_FIFO.v
DE2_TV/Sdram_Control_4Port/Sdram_WR_FIFO.qip
DE2_TV/Sdram_Control_4Port/Sdram_WR_FIFO.v
DE2_TV/Sdram_Control_4Port/sdr_data_path.v
DE2_TV/Sdram_PLL.qip
DE2_TV/Sdram_WR_FIFO.qip
DE2_TV/v/AUDIO_DAC.v
DE2_TV/v/DIV.v
DE2_TV/v/I2C_AV_Config.v
DE2_TV/v/I2C_Controller.v
DE2_TV/v/ITU_656_Decoder.v
DE2_TV/v/Line_Buffer.v
DE2_TV/v/MAC_3.v
DE2_TV/v/PLL.v
DE2_TV/v/Reset_Delay.v
DE2_TV/v/SEG7_LUT.v
DE2_TV/v/SEG7_LUT_8.v
DE2_TV/v/TD_Detect.v
DE2_TV/v/TP_RAM.v
DE2_TV/v/VGA_Ctrl.v
DE2_TV/v/YCbCr2RGB.v
DE2_TV/v/YUV422_to_444.v
DE2_TV/Sdram_Control_4Port/greybox_tmp
DE2_TV/demo_batch
DE2_TV/greybox_tmp
DE2_TV/Sdram_Control_4Port
DE2_TV/v
DE2_TV
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