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文件名称:T01_UART_CORE

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [C/C++] [源码]
  • 上传时间：
    2014-11-15
  • 文件大小：
    413.71kb
  • 已下载：
    0次
  • 提 供 者：
    FEI***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

Verilog 实现的 UART串口读写控制核 参数化校验、时钟设置，完整工程（xilinx），包括文档、源码等。供学习参考，希望大家上传自己代码，共同提高，打倒小日本。-Verilog implementation of the UART serial port to read and write control nuclear parametric check, clock setting, complete project (Xilinx), including documentation, source code and so on. For learning reference, hope you upload your own code, improve together, little japanese.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

T01_UART_CORE/
T01_UART_CORE/01_Xilinx_Pro/
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/fuse.log
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/fuse.xmsgs
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/fuseRelaunch.cmd
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/ipcore_dir/
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/iseconfig/
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/iseconfig/UART_CORE.projectmgr
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/iseconfig/UART_CORE.xreport
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim/
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim.cmd
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim.log
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim/isim_usage_statistics.html
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim/pn_info
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim/temp/
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim/temp/@test_@u@a@r@t_@c@o@r@e.sdb
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim/temp/@u@a@r@t_@c@o@r@e.sdb
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim/temp/glbl.sdb
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim/Test_UART_CORE_isim_beh.exe.sim/
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim/Test_UART_CORE_isim_beh.exe.sim/isimcrash.log
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim/Test_UART_CORE_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim/Test_UART_CORE_isim_beh.exe.sim/isimkernel.log
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim/Test_UART_CORE_isim_beh.exe.sim/netId.dat
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim/Test_UART_CORE_isim_beh.exe.sim/Test_UART_CORE_isim_beh.exe
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim/Test_UART_CORE_isim_beh.exe.sim/tmp_save/
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim/Test_UART_CORE_isim_beh.exe.sim/tmp_save/_1
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim/Test_UART_CORE_isim_beh.exe.sim/work/
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim/Test_UART_CORE_isim_beh.exe.sim/work/m_00000000000725662178_2338868275.c
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim/Test_UART_CORE_isim_beh.exe.sim/work/m_00000000000725662178_2338868275.didat
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim/Test_UART_CORE_isim_beh.exe.sim/work/m_00000000000725662178_2338868275.nt.obj
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim/Test_UART_CORE_isim_beh.exe.sim/work/m_00000000001158853363_1099395310.c
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim/Test_UART_CORE_isim_beh.exe.sim/work/m_00000000001158853363_1099395310.didat
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim/Test_UART_CORE_isim_beh.exe.sim/work/m_00000000001158853363_1099395310.nt.obj
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim/Test_UART_CORE_isim_beh.exe.sim/work/m_00000000004093713498_2073120511.c
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim/Test_UART_CORE_isim_beh.exe.sim/work/m_00000000004093713498_2073120511.didat
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim/Test_UART_CORE_isim_beh.exe.sim/work/m_00000000004093713498_2073120511.nt.obj
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim/Test_UART_CORE_isim_beh.exe.sim/work/Test_UART_CORE_isim_beh.exe_main.c
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim/Test_UART_CORE_isim_beh.exe.sim/work/Test_UART_CORE_isim_beh.exe_main.nt.obj
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim/work/
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim/work/@test_@u@a@r@t_@c@o@r@e.sdb
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim/work/@u@a@r@t_@c@o@r@e.sdb
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/isim/work/glbl.sdb
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/Test_UART_CORE_beh.prj
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/Test_UART_CORE_isim_beh.exe
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/Test_UART_CORE_isim_beh.wdb
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/Test_UART_CORE_stx_beh.prj
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/UART_CORE.bld
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/UART_CORE.cmd_log
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/UART_CORE.gise
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/UART_CORE.lso
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/UART_CORE.ngc
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/UART_CORE.ngd
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/UART_CORE.ngr
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/UART_CORE.prj
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/UART_CORE.stx
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/UART_CORE.syr
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/UART_CORE.xise
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/UART_CORE.xst
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/UART_CORE_envsettings.html
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/UART_CORE_ngdbuild.xrpt
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/UART_CORE_summary.html
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/UART_CORE_xst.xrpt
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/webtalk_pn.xml
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/xilinxsim.ini
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/xlnx_auto_0_xdb/
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/xlnx_auto_0_xdb/cst.xbcd
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/xst/
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/xst/dump.xst/
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/xst/dump.xst/UART_CORE.prj/
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/xst/projnav.tmp/
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/xst/work/
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/xst/work/work.sdbl
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/xst/work/work.sdbx
T01_UART_CORE/01_Xilinx_Pro/UART_CORE/_ngo/
T01

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