labmic_soc/firmware/lib/hal_io.c
labmic_soc/firmware/lib/hal_uart.c
labmic_soc/firmware/lib/stdint.h
labmic_soc/firmware/lib/printf.c
labmic_soc/firmware/lib/stdio.h
labmic_soc/firmware/lib/hal_uart.h
labmic_soc/firmware/lib/memory_map.h
labmic_soc/firmware/lib/hal_io.h
labmic_soc/firmware/lib/.deps/pic.Po
labmic_soc/firmware/lib/.deps/hal_io.Po
labmic_soc/firmware/lib/.deps/printf.Po
labmic_soc/firmware/lib/.deps/hal_uart.Po
labmic_soc/firmware/led_keyboard.c
labmic_soc/firmware/Makefile
labmic_soc/fpga/cores/memory/dpram32_coregen.v
labmic_soc/fpga/cores/memory/mem_delay_gen.v
labmic_soc/fpga/cores/memory/medfifo.v
labmic_soc/fpga/cores/memory/ram_harvard_coregen.v
labmic_soc/fpga/cores/memory/longfifo.v
labmic_soc/fpga/cores/memory/shortfifo.v
labmic_soc/fpga/cores/memory/srl.v
labmic_soc/fpga/cores/aemb/rtl/verilog/aeMB_sim.v
labmic_soc/fpga/cores/aemb/rtl/verilog/aeMB_edk32_virtex6.v
labmic_soc/fpga/cores/aemb/rtl/verilog/aeMB_ibuf_virtex6.v
labmic_soc/fpga/cores/aemb/rtl/verilog/aeMB_regf.v
labmic_soc/fpga/cores/aemb/rtl/verilog/aeMB_core_virtex6.v
labmic_soc/fpga/cores/aemb/rtl/verilog/aeMB_ctrl.v
labmic_soc/fpga/cores/aemb/rtl/verilog/aeMB_core.v
labmic_soc/fpga/cores/aemb/rtl/verilog/aeMB_bpcu.v
labmic_soc/fpga/cores/aemb/rtl/verilog/aeMB_xecu.v
labmic_soc/fpga/cores/aemb/rtl/verilog/aeMB_core_BE.v
labmic_soc/fpga/cores/aemb/rtl/verilog/aeMB_edk32.v
labmic_soc/fpga/cores/aemb/rtl/verilog/aeMB_ibuf.v
labmic_soc/fpga/cores/aemb/rtl/verilog/aeMB_core_BE_virtex6.v
labmic_soc/fpga/cores/aemb/sw/c/endian-test.c
labmic_soc/fpga/cores/aemb/sw/c/aeMB_testbench.c
labmic_soc/fpga/cores/aemb/sw/c/libaemb.h
labmic_soc/fpga/cores/aemb/sw/gccrom
labmic_soc/fpga/cores/aemb/sim/verilog/aemb2.v
labmic_soc/fpga/cores/aemb/sim/verilog/edk32.v
labmic_soc/fpga/cores/aemb/sim/iversim
labmic_soc/fpga/cores/aemb/sim/CODE_DEBUG.sav
labmic_soc/fpga/cores/aemb/sim/cversim
labmic_soc/fpga/cores/aemb/doc/aeMB_datasheet.pdf
labmic_soc/fpga/cores/Makefile.srcs
labmic_soc/fpga/cores/bus/wb_1master.v
labmic_soc/fpga/cores/example/wishbone_example.v
labmic_soc/fpga/cores/control/system_control.v
labmic_soc/fpga/cores/control/ram_loader_uart.v
labmic_soc/fpga/cores/uart/simple_uart_rx.v
labmic_soc/fpga/cores/uart/simple_uart.v
labmic_soc/fpga/cores/uart/simple_uart_tx.v
labmic_soc/fpga/models/xlnx_glbl.v
labmic_soc/fpga/models/uart_rx.v
labmic_soc/fpga/models/RAMB16_S36_S36.v
labmic_soc/fpga/models/FIFO_GENERATOR_V4_3.v
labmic_soc/fpga/models/M24LC024B.v
labmic_soc/fpga/models/Makefile.srcs
labmic_soc/fpga/models/math_real.v
labmic_soc/fpga/models/SRL16E.v
labmic_soc/fpga/models/SRLC16E.v
labmic_soc/fpga/models/uart_host.v
labmic_soc/fpga/models/M24LC02B.v
labmic_soc/fpga/models/BUFG.v
labmic_soc/fpga/models/host_bootloader_model.v
labmic_soc/fpga/models/BLK_MEM_GEN_V4_1.v
labmic_soc/fpga/models/BLK_MEM_GEN_V6_1.v
labmic_soc/fpga/models/MULT18X18S.v
labmic_soc/fpga/models/FIFO_GENERATOR_V6_1.v
labmic_soc/fpga/coregen/ram_xlnx_4k_dp.gise
labmic_soc/fpga/coregen/coregen.cgc
labmic_soc/fpga/coregen/ram_xlnx_4k_dp_flist.txt
labmic_soc/fpga/coregen/clk_xlnx_100M.v
labmic_soc/fpga/coregen/clk_xlnx_100M_flist.txt
labmic_soc/fpga/coregen/ram_xlnx_4k_dp.v
labmic_soc/fpga/coregen/clk_xlnx_100M.xaw
labmic_soc/fpga/coregen/ram_xlnx_4k_dp.ncf
labmic_soc/fpga/coregen/ram_xlnx_4k_dp.ngc
labmic_soc/fpga/coregen/ram_xlnx_4k_dp.veo
labmic_soc/fpga/coregen/Makefile.srcs
labmic_soc/fpga/coregen/coregen.log
labmic_soc/fpga/coregen/blk_mem_gen_ds512.pdf
labmic_soc/fpga/coregen/xaw2verilog.log
labmic_soc/fpga/coregen/clk_xlnx_100M_arwz.ucf
labmic_soc/fpga/coregen/_xmsgs/pn_parser.xmsgs
labmic_soc/fpga/coregen/ram_xlnx_4k_dp.xise
labmic_soc/fpga/coregen/ram_xlnx_4k_dp.xco
labmic_soc/fpga/coregen/ram_xlnx_4k_dp_xmdf.tcl
labmic_soc/fpga/coregen/coregen.cgp
labmic_soc/fpga/coregen/blk_mem_gen_readme.txt
labmic_soc/fpga/testbench/wb_soc.do
labmic_soc/fpga/testbench/Makefile
labmic_soc/fpga/toplevel/Makefile.common
labmic_soc/fpga/toplevel/wb_soc/wb_soc_spartan3.impact
labmic_soc/fpga/toplevel/wb_soc/wb_soc_spartan3.cdf
labmic_soc/fpga/toplevel/wb_soc/wb_soc_spartan3.ucf
labmic_soc/fpga/toplevel/wb_soc/wb_soc_sim.v
labmic_soc/fpga/toplevel/wb_soc/wb_soc.v
labmic_soc/fpga/toplevel/wb_soc/Makefile
labmic_soc/fpga/toplevel/wb_soc/wb_soc_spartan3.v
labmic_soc/fpga/toplevel/tcl/ise_helper.tcl
labmic_soc/bootloader/main.c
labmic_soc/bootloader/includes/linux_uart_device.h
labmic_soc/bootloader/includes/protocol.h
labmic_soc/bootloader/includes/device.h
labmic_soc/bootloader/includes/standard_output.h
labmic_soc/bootloader/Makefile
labmic_soc/bootloader/ml605_loader
labmic_soc/bootloader/main.o
labmic_soc/fpga/cores/aemb/rtl/verilog
labmic_soc/fpga/cores/aemb/sw/c
labmic_soc/fpga/cores/aemb/sim/verilog
labmic_soc/fpga/cores/aemb/rtl
labmic_soc/fpga/cores/aemb/sw
labmic_soc/fpga/cores/aemb/sim
labmic_soc/fpga/cores/aemb/doc
labmic_soc/firmware/lib/.deps
labmic_soc/fpga/cores/memory
labmic_soc/fpga/cores/aemb
labmic_soc/fpga/cores/bus
labmic_soc/fpga/cores/example
labmic_soc/fpga/cores/control
labmic_soc/fpga/cores/uart
labmic_soc/fpga/coregen/_xmsgs
labmic_soc/fpga/toplevel/wb_soc
labmic