一个VHDL编的简单乘法器，基本原理设计如下图所示: 将两个操作数分别以串行和并行模式输入到乘法器的输入端, 用串行输入操作数的每一位依次去乘并行输入的操作数, 每次的结果称之为部分积, 将每次相乘得到的部分积加到累加器里, 形成部分和, 部分和在与下一个部分积相加前要进行移位操作。-A simple multiplier VHDL series, the basic principles of design as follows: two operands, respectively, serial and parallel mode to the input terminal of the multiplier, with every serial input operands in parallel in order to multiply the input operands, the result of each partial product is called, the partial products obtained by multiplying each time to the accumulator, the forming portion, and, prior to the addition portion and with the next partial product is shifted to .